From a780345e014196231e6d9e15c328c0aadeaa02f3 Mon Sep 17 00:00:00 2001
From: Rhys Perry <pendingchaos02@gmail.com>
Date: Tue, 25 Mar 2025 14:41:47 +0000
Subject: [PATCH] aco: fix compact_relocate_vars fallback with scc/exec/m0
 precolored regs
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This probably doesn't fix anything in practice. I don't think this path is
ever taken for SGPRs except for pseudo-scalar transcendental instructions,
and those don't have any precolored operands/definitions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34343>
---
 src/amd/compiler/aco_register_allocation.cpp | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 518927c0514..e8e19efb87a 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1886,20 +1886,28 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
    if (!increase_register_file(ctx, info.rc)) {
       /* fallback algorithm: reallocate all variables at once (linear VGPRs should already be
        * compact at the end) */
+      const PhysRegInterval regs = get_reg_bounds(ctx, info.rc);
+
       unsigned def_size = info.rc.size();
       for (Definition def : instr->definitions) {
+         if (def.isPrecolored()) {
+            assert(!regs.contains({def.physReg(), def.size()}));
+            continue;
+         }
          if (ctx.assignments[def.tempId()].assigned && def.regClass().type() == info.rc.type())
             def_size += def.regClass().size();
       }
 
       unsigned killed_op_size = 0;
       for (Operand op : instr->operands) {
+         if (op.isPrecolored()) {
+            assert(!regs.contains({op.physReg(), op.size()}));
+            continue;
+         }
          if (op.isTemp() && op.isFirstKillBeforeDef() && op.regClass().type() == info.rc.type())
             killed_op_size += op.regClass().size();
       }
 
-      const PhysRegInterval regs = get_reg_bounds(ctx, info.rc);
-
       /* reallocate passthrough variables and non-killed operands */
       std::vector<IDAndRegClass> vars;
       for (unsigned id : find_vars(ctx, reg_file, regs))
@@ -1911,7 +1919,8 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
       /* reallocate killed operands */
       std::vector<IDAndRegClass> killed_op_vars;
       for (Operand op : instr->operands) {
-         if (op.isFirstKillBeforeDef() && op.regClass().type() == info.rc.type())
+         if (!op.isPrecolored() && op.isFirstKillBeforeDef() &&
+             op.regClass().type() == info.rc.type())
             killed_op_vars.emplace_back(op.tempId(), op.regClass());
       }
       compact_relocate_vars(ctx, killed_op_vars, parallelcopies, space);
@@ -1919,7 +1928,8 @@ get_reg(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp,
       /* reallocate definitions */
       std::vector<IDAndRegClass> def_vars;
       for (Definition def : instr->definitions) {
-         if (ctx.assignments[def.tempId()].assigned && def.regClass().type() == info.rc.type())
+         if (!def.isPrecolored() && ctx.assignments[def.tempId()].assigned &&
+             def.regClass().type() == info.rc.type())
             def_vars.emplace_back(def.tempId(), def.regClass());
       }
       def_vars.emplace_back(0xffffffff, info.rc);