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aco/ra: don't require alignment for NPOT SGPR temporaries

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Aligning these can create situations where register allocation is
impossible. Only pseudo-instructions can use these, and they don't require
any alignment.

I'm not sure if these temporaries actually happen in practice. This
probably only affects the get_reg()'s compact_relocate_vars fallback path,
which doesn't usually happen for SGPRs.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34343>
This commit is contained in:
Rhys Perry
2025-04-25 13:48:36 +01:00
committed by Marge Bot
parent 623230a6ef
commit f6581b41c4
1 changed files with 3 additions and 1 deletions
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src/amd/compiler/aco_register_allocation.cpp
+3 -1
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@@ -200,7 +200,7 @@ get_stride(RegClass rc)
uint32_t size = rc.size();
if (size == 2) {
return 2;
} else if (size >= 4) {
} else if (size >= 4 && util_is_power_of_two_or_zero(size)) {
return 4;
} else {
return 1;
@@ -1545,6 +1545,8 @@ compact_relocate_vars(ra_ctx& ctx, const std::vector<IDAndRegClass>& vars,
assert(a.info.rc.type() != RegType::sgpr || get_reg_bounds(ctx, a.info.rc).size % 2 == 0);
assert(a_stride == 16 || a_stride == 8 || a_stride == 4);
assert(b_stride == 16 || b_stride == 8 || b_stride == 4);
assert(a.info.rc.size() % (a_stride / 4u) == 0);
assert(b.info.rc.size() % (b_stride / 4u) == 0);
if ((a_stride == 16) != (b_stride == 16))
return a_stride > b_stride;
if (a.id == 0xffffffff || b.id == 0xffffffff)