From f6581b41c4cb5b284f5550c7494d67ca37b391e6 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 25 Apr 2025 13:48:36 +0100 Subject: [PATCH] aco/ra: don't require alignment for NPOT SGPR temporaries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Aligning these can create situations where register allocation is impossible. Only pseudo-instructions can use these, and they don't require any alignment. I'm not sure if these temporaries actually happen in practice. This probably only affects the get_reg()'s compact_relocate_vars fallback path, which doesn't usually happen for SGPRs. Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_register_allocation.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 942730ad346..518927c0514 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -200,7 +200,7 @@ get_stride(RegClass rc) uint32_t size = rc.size(); if (size == 2) { return 2; - } else if (size >= 4) { + } else if (size >= 4 && util_is_power_of_two_or_zero(size)) { return 4; } else { return 1; @@ -1545,6 +1545,8 @@ compact_relocate_vars(ra_ctx& ctx, const std::vector& vars, assert(a.info.rc.type() != RegType::sgpr || get_reg_bounds(ctx, a.info.rc).size % 2 == 0); assert(a_stride == 16 || a_stride == 8 || a_stride == 4); assert(b_stride == 16 || b_stride == 8 || b_stride == 4); + assert(a.info.rc.size() % (a_stride / 4u) == 0); + assert(b.info.rc.size() % (b_stride / 4u) == 0); if ((a_stride == 16) != (b_stride == 16)) return a_stride > b_stride; if (a.id == 0xffffffff || b.id == 0xffffffff)