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radv: enable DCC fast clears for 8bpp/16bpp on GFX11

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This was disabled during GFX11 bringup few years ago to follow RadeonSI,
but this is working just fine and RadeonSI also enabled it recently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33756>
This commit is contained in:
Samuel Pitoiset
2025-02-26 09:48:26 +01:00
committed by Marge Bot
parent aa476f4b52
commit 3c81961c2e
1 changed files with 0 additions and 4 deletions
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src/amd/vulkan/meta/radv_meta_clear.c
-4
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@@ -1253,10 +1253,6 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im
unsigned start_bit = UINT_MAX;
unsigned end_bit = 0;
/* TODO: 8bpp and 16bpp fast DCC clears don't work. */
if (desc->block.bits <= 16)
return false;
/* Find the used bit range. */
for (unsigned i = 0; i < 4; i++) {
unsigned swizzle = desc->swizzle[i];