From 3c81961c2e2fa3e8bacf85114871d881024fc002 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 26 Feb 2025 09:48:26 +0100 Subject: [PATCH] radv: enable DCC fast clears for 8bpp/16bpp on GFX11 This was disabled during GFX11 bringup few years ago to follow RadeonSI, but this is working just fine and RadeonSI also enabled it recently. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta_clear.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 13bc74cbf74..50bfa2210b7 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -1253,10 +1253,6 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im unsigned start_bit = UINT_MAX; unsigned end_bit = 0; - /* TODO: 8bpp and 16bpp fast DCC clears don't work. */ - if (desc->block.bits <= 16) - return false; - /* Find the used bit range. */ for (unsigned i = 0; i < 4; i++) { unsigned swizzle = desc->swizzle[i];