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radv: use common scratch tmpring size programming

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No logical changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34549>
This commit is contained in:
Samuel Pitoiset
2025-04-16 13:09:49 +02:00
committed by Marge Bot
parent 710d7ea8b8
commit 11e8a96495
1 changed files with 9 additions and 11 deletions
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src/amd/vulkan/radv_queue.c
+9 -11
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@@ -492,10 +492,13 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radeon_info *gpu_info = &pdev->info;
uint32_t tmpring_size;
if (!scratch_bo)
return;
ac_get_scratch_tmpring_size(gpu_info, waves, size_per_wave, &tmpring_size);
radv_cs_add_buffer(device->ws, cs, scratch_bo);
radeon_begin(cs);
@@ -503,18 +506,12 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
if (gpu_info->gfx_level >= GFX11) {
uint64_t va = radv_buffer_get_va(scratch_bo);
/* WAVES is per SE for SPI_TMPRING_SIZE. */
waves /= gpu_info->max_se;
radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
radeon_emit(S_0286E8_WAVES(waves) |
S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, gpu_info->scratch_wavesize_granularity)));
radeon_emit(tmpring_size);
radeon_emit(va >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
radeon_emit(va >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
} else {
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE,
S_0286E8_WAVES(waves) |
S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, gpu_info->scratch_wavesize_granularity)));
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, tmpring_size);
}
radeon_end();
@@ -526,6 +523,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radeon_info *gpu_info = &pdev->info;
uint32_t tmpring_size;
uint64_t scratch_va;
uint32_t rsrc1;
@@ -540,6 +538,8 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
else
rsrc1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1);
ac_get_scratch_tmpring_size(gpu_info, waves, size_per_wave, &tmpring_size);
radv_cs_add_buffer(device->ws, cs, compute_scratch_bo);
radeon_begin(cs);
@@ -556,9 +556,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
radeon_emit(scratch_va);
radeon_emit(rsrc1);
radeon_set_sh_reg(
R_00B860_COMPUTE_TMPRING_SIZE,
S_00B860_WAVES(waves) | S_00B860_WAVESIZE(DIV_ROUND_UP(size_per_wave, gpu_info->scratch_wavesize_granularity)));
radeon_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE, tmpring_size);
radeon_end();
}