From 11e8a9649566b9a032a86da6fe617d350fd4e549 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 16 Apr 2025 13:09:49 +0200 Subject: [PATCH] radv: use common scratch tmpring size programming No logical changes. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_queue.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 7ce7b68cfc4..0d8fda7cc82 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -492,10 +492,13 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, { const struct radv_physical_device *pdev = radv_device_physical(device); const struct radeon_info *gpu_info = &pdev->info; + uint32_t tmpring_size; if (!scratch_bo) return; + ac_get_scratch_tmpring_size(gpu_info, waves, size_per_wave, &tmpring_size); + radv_cs_add_buffer(device->ws, cs, scratch_bo); radeon_begin(cs); @@ -503,18 +506,12 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, if (gpu_info->gfx_level >= GFX11) { uint64_t va = radv_buffer_get_va(scratch_bo); - /* WAVES is per SE for SPI_TMPRING_SIZE. */ - waves /= gpu_info->max_se; - radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3); - radeon_emit(S_0286E8_WAVES(waves) | - S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, gpu_info->scratch_wavesize_granularity))); + radeon_emit(tmpring_size); radeon_emit(va >> 8); /* SPI_GFX_SCRATCH_BASE_LO */ radeon_emit(va >> 40); /* SPI_GFX_SCRATCH_BASE_HI */ } else { - radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, - S_0286E8_WAVES(waves) | - S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, gpu_info->scratch_wavesize_granularity))); + radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, tmpring_size); } radeon_end(); @@ -526,6 +523,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, { const struct radv_physical_device *pdev = radv_device_physical(device); const struct radeon_info *gpu_info = &pdev->info; + uint32_t tmpring_size; uint64_t scratch_va; uint32_t rsrc1; @@ -540,6 +538,8 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, else rsrc1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1); + ac_get_scratch_tmpring_size(gpu_info, waves, size_per_wave, &tmpring_size); + radv_cs_add_buffer(device->ws, cs, compute_scratch_bo); radeon_begin(cs); @@ -556,9 +556,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, radeon_emit(scratch_va); radeon_emit(rsrc1); - radeon_set_sh_reg( - R_00B860_COMPUTE_TMPRING_SIZE, - S_00B860_WAVES(waves) | S_00B860_WAVESIZE(DIV_ROUND_UP(size_per_wave, gpu_info->scratch_wavesize_granularity))); + radeon_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE, tmpring_size); radeon_end(); }