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Author SHA1 Message Date
Martin Krastev
fec6ef6d7f svga/ci: drop FDO_CI_CONCURRENT to 1 
* drop FDO_CI_CONCURRENT to 1; eliminate intermittent piglit concurrecy issues
* bump PIGLIT_FRACTION to 2; lowering concurrency increases exec time, so
  for now compensate with job fraction set to 50%
* triage piglit failures

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32526>
 2024-12-06 16:38:43 +00:00
Martin Krastev
82d2e1df6c svga/ci: update svga/ci KERNEL_TAG 
A new kernel build was provided, update the KERNEL_TAG accordingly.

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32526>
 2024-12-06 16:38:43 +00:00
Martin Krastev
2f3335d878 svga/ci: triage piglit failures 
Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32526>
 2024-12-06 16:38:43 +00:00
Martin Krastev
3cf17feb2a svga/ci: set vmware piglit job parallelism to 2 
Job parallelism controls the number of DUTs employed by the job.
As vmware CI farm enabled multiple DUTs recently, bump this to 2
DUTs for the time being.

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32526>
 2024-12-06 16:38:43 +00:00
Martin Krastev
5f31cec10a svga/ci: enable vmware farm 
* enable vmware farm after maintenance
* update svga/ci KERNEL_TAG

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32526>
 2024-12-06 16:38:43 +00:00
Tomeu Vizoso
da77188d7d etnaviv/ml: Implement FullyConnected 
Lower FullyConnected to a regular convolution so it executes in the NN
cores.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32510>
 2024-12-06 16:03:05 +00:00
Tomeu Vizoso
ad82a7c388 teflon: Add tests for FullyConnected 
Same as we do with convolutions and additions.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32510>
 2024-12-06 16:03:05 +00:00
Tomeu Vizoso
3d8f108514 teflon: Add support for FullyConnected 
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32510>
 2024-12-06 16:03:05 +00:00
Tomeu Vizoso
3e74234450 etnaviv/ml: Add support for tensor padding operations 
Just one more TP operation, at least for the pad modes supported.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32509>
 2024-12-06 15:09:52 +00:00
Tomeu Vizoso
02e92bbcea teflon: Add support for tensor padding operations 
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32509>
 2024-12-06 15:09:52 +00:00
Daniel Schürmann
b64fff7731 aco: remove definition from Pseudo branch instructions 
They are not needed anymore.

Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)

Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Daniel Schürmann
7e4687fd04 aco: remove definition from SOPP branch instructions 
Totals from 17942 (22.60% of 79395) affected shaders: (Navi31)

Instrs: 20334063 -> 20312676 (-0.11%); split: -0.11%, +0.00%
CodeSize: 108458732 -> 108377540 (-0.07%); split: -0.08%, +0.00%
Latency: 180510540 -> 180479666 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 28079325 -> 28077938 (-0.00%); split: -0.01%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Daniel Schürmann
cab5639a09 aco/assembler: chain branches instead of emitting long jumps 
As regular branch instructions cannot jump further than
32768 dwords, previously we used long jumps as fallback
solution. The disadvantage of that is that an extra SGPR
pair must be provided in order to temporarily store the PC.

This patch changes that to chained branch instructions by
inserting an artificial extra block into the code to be
targeted by the original branch. This block contains a
single branch instruction jumping to the original target.
Before the block, if necessary, we insert a <branch 1>
instruction for the existing code in order to jump over
the newly inserted block.

Only a few RT shaders are affected.

Totals from 29 (0.04% of 79395) affected shaders: (Navi31)

CodeSize: 17281176 -> 17276332 (-0.03%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Daniel Schürmann
c3d777d8ac aco/assembler: change ctx.loop_header to uint32_t instead of Block* 
We are about to add new blocks during assembly which makes
pointers into a vector unreliable.
Also, only set it if the loop has no back-edge.

Totals from 126 (0.16% of 79206) affected shaders: (Navi31)

CodeSize: 1486152 -> 1488152 (+0.13%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Daniel Schürmann
592f3fd994 aco/assembler: Actually insert s_inst_prefetch instructions when aligning blocks for loops 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Daniel Schürmann
b92afdbd28 aco/assembler: constify assembly functions 
Ensure that instruction formats and special operands
are not manipulated during assembly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Daniel Schürmann
3a02bbd916 aco/print_asm: allow for empty blocks with arbitrary offsets 
We will add empty blocks at the end of the shader,
in order to store some branch offset information.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
 2024-12-06 14:34:03 +00:00
Rhys Perry
ab26b99c2c aco: don't CSE p_shader_cycles_hi_lo_hi 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: fae2a85d57 ("aco/gfx12: implement subgroup shader clock")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12243
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32500>
 2024-12-06 14:06:05 +00:00
Tomeu Vizoso
6c70b10f03 etna/ml: Write out the size of the requested tensor 
Instead of the size of its backing resource.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Tomeu Vizoso
fe08834004 teflon: Limit support for Add to two unpopulated tensors 
As the only implementations depend of both inputs coming from
convolutions.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Tomeu Vizoso
c2d1f08116 etnaviv/ml: Add support for tensor split and concatenation operations 
Just point previous and further operations to offsets in a combined
tensor.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Tomeu Vizoso
4ced6480ea teflon: Add support for tensor split and concatenation operations 
These are often use to reuse the output from a previous operation, or to
implement convolution groups.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Tomeu Vizoso
418f864ae4 etnaviv/ml: Take offsets into account in TP operations 
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Tomeu Vizoso
566166b0aa etnaviv/ml: Fix in_image_slice in transposes when width != height 
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Tomeu Vizoso
10bd5c23c6 etnaviv/ml: Specify which of the input tensors need transposing. 
In preparation for operations that have more than one input that may
need transposing, such as Add.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32498>
 2024-12-06 13:29:11 +00:00
Georg Lehmann
d47deba142 zink: spec@ext_framebuffer_multisample@blit-mismatched-formats was fixed 
Fixed in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31378

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32522>
 2024-12-06 12:58:47 +00:00
Georg Lehmann
da4b9ac4a5 radeonsi/ci: add vangogh ubo fail 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32522>
 2024-12-06 12:58:47 +00:00
Georg Lehmann
b2464e3609 aco/gfx12+: do not use v_pack_b32_f16 to pack untyped data 
GFX12 removed IEEE_MODE, and made its signalling NaN quieting the default.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12251
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32502>
 2024-12-06 12:33:05 +00:00
Georg Lehmann
7425e71ae0 aco/gfx12: disable vinterp ddx/ddy optimization 
This only seems to work on gfx11 and gfx11.5, and it's only faster on gfx11.5.

We could continue to use vinterp, with constants copied to vgprs, but
whether that's beneficial depends on the shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Fixes: bee487df48 ("aco/gfx11.5+: use vinterp for fddx/fddy")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12250
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32495>
 2024-12-06 12:01:39 +00:00
David Rosca
3dd6ddde3b radeonsi/vcn: Cleanup JPEG supported formats 
Stop reporting L8_UNORM as supported.
Remove unsupported IYUV, YV12, P010 and P016 formats from list,
add rest of the supported formats and add assert.

Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504>
 2024-12-06 11:24:53 +00:00
David Rosca
22ced06ee6 radeonsi/vcn: Make sure JPEG target buffer format matches sampling factor 
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504>
 2024-12-06 11:24:53 +00:00
David Rosca
1a7d956c75 radeonsi/vcn: Gracefully handle decode errors and report to frontend 
Previously it would print error message and then most likely crash later.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504>
 2024-12-06 11:24:53 +00:00
David Rosca
9a3a1027a6 radeonsi/vcn: Unmap bitstream buffer in radeon_dec_destroy 
If an error occured, the bitstream buffer may still be mapped when
calling radeon_dec_destroy and this would trigger assert when destroying
the bo.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504>
 2024-12-06 11:24:53 +00:00
David Rosca
ed5794c5e3 radeonsi/vcn: Remove code handling buffer_get_virtual_address failure 
buffer_get_virtual_address can't return zero.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504>
 2024-12-06 11:24:53 +00:00
David Rosca
5f3a93dacf frontends/va: Move mjpeg sampling_factor to pipe_mjpeg_picture_desc 
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504>
 2024-12-06 11:24:53 +00:00
Benjamin Lee
7a9f14d3c2 panvk: advertise VK_EXT_provoking_vertex 
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273>
 2024-12-06 10:40:03 +00:00
Benjamin Lee
fec20b26dd panvk: set provoking vertex in fbinfo 
This must match the value set in TILER_CONTEXT. Fixes
dEQP-VK.rasterization.flatshading.*, which were failing previously
because we were setting first_provoking_vertex to true in the tiler
descriptor and false in fbinfo.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273>
 2024-12-06 10:40:03 +00:00
Benjamin Lee
c324790ca8 panvk: treat provoking vertex as dynamic state 
Needed for VK_EXT_provoking_vertex, and makes the fbinfo provoking
vertex requirements easier to follow.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273>
 2024-12-06 10:40:03 +00:00
Benjamin Lee
c383859a07 panvk: refactor fbinfo into a temp var in get_tiler_desc 
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273>
 2024-12-06 10:40:03 +00:00
David Rosca
1a90c3102b radeonsi/vcn: Don't allow encoding H264 B-frame references 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12242

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32479>
 2024-12-06 10:00:47 +00:00
David Rosca
cd8ad03364 frontends/va: Store picture type for buffers in encode DPB 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32479>
 2024-12-06 10:00:47 +00:00
Friedrich Vock
c2f8f20ef7 radv,driconf: Apply DOOM Eternal/idTech workarounds for Indiana Jones 
It's based on idTech and exhibits the same idTech bugs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32521>
 2024-12-06 09:21:17 +00:00
Karmjit Mahil
047049dcb5 nir: Fix the spelling of compare 
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32189>
 2024-12-06 08:42:36 +00:00
Karmjit Mahil
b79994e92d nir,ir3: Add icsel_eqz 
In IR3 `sel.b32` works based on the 0 so add `icsel_eqz` to fuse the
cmp and sel that we'd otherwise need.

total Instruction Count in shared programs: 1112814 -> 1110473 (-0.21%)
Instruction Count in affected programs: 162701 -> 160360 (-1.44%)
helped: 81
HURT: 29
Instruction count are helped.

total MOV Count in shared programs: 86777 -> 88671 (2.18%)
MOV Count in affected programs: 28119 -> 30013 (6.74%)
helped: 1
HURT: 292
Mov count are HURT.

total COV Count in shared programs: 15070 -> 14962 (-0.72%)
COV Count in affected programs: 5770 -> 5662 (-1.87%)
helped: 76
HURT: 2
Cov count are helped.

total Last helper instruction in shared programs: 592729 -> 590638 (-0.35%)
Last helper instruction in affected programs: 91331 -> 89240 (-2.29%)
helped: 30
HURT: 1
Last helper instruction are helped.

total Instructions with SS sync bit in shared programs: 29336 -> 29546 (0.72%)
Instructions with SS sync bit in affected programs: 4702 -> 4912 (4.47%)
helped: 8
HURT: 43
Instructions with ss sync bit are HURT.

total Estimated cycles stalled on SS in shared programs: 111590 -> 112401 (0.73%)
Estimated cycles stalled on SS in affected programs: 27708 -> 28519 (2.93%)
helped: 21
HURT: 61
Estimated cycles stalled on ss are HURT.

total cat1 instructions in shared programs: 101933 -> 103695 (1.73%)
cat1 instructions in affected programs: 35804 -> 37566 (4.92%)
helped: 18
HURT: 290
Cat1 instructions are HURT.

total cat2 instructions in shared programs: 380299 -> 377499 (-0.74%)
cat2 instructions in affected programs: 128609 -> 125809 (-2.18%)
helped: 322
HURT: 0
Cat2 instructions are helped.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32189>
 2024-12-06 08:42:36 +00:00
Karmjit Mahil
aad0aa0a9c nir/algebraic: turn u{ge,lt} a, 1 to i{ne,eq} a, 0 
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32189>
 2024-12-06 08:42:36 +00:00
Samuel Pitoiset
6b671d4dab radv: remove redundant drirc for incorrect dual-source blending 
The pass that lowers PS outputs has been rewritten since 45d8cd037a
("ac/nir: rewrite ac_nir_lower_ps epilog to fix dual src blending
with mono PS") to handle invalid uses of dual-source blending.

This drirc used to workaround game bugs on GFX11 only should no longer
be necessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32514>
 2024-12-06 07:54:23 +00:00
Ian Romanick
e1bb53bb3c nir/algebraic: Optimize some trivial bfi 
In fossil-db, one big compute shader on Hogwarts Legacy is helped for
spills and fills. It has a lot of instances of bfi(0x3f, a, a).

On Tiger Lake and Skylake, a compute shader in Unicom that has a
single instance of this pattern is hurt for spills and fills. I think
this is just due to non-determinism in the register allocation
algorithm.

shader-db:

All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 16992643 -> 16992548 (<.01%)
instructions in affected programs: 17533 -> 17438 (-0.54%)
helped: 33 / HURT: 0

total cycles in shared programs: 914313986 -> 914316238 (<.01%)
cycles in affected programs: 3734544 -> 3736796 (0.06%)
helped: 26 / HURT: 6

fossil-db:

Lunar Lake, Meteor Lake, DG2, and Ice Lake had similar results. (Lunar Lake shown)
Totals:
Instrs: 208952780 -> 208952537 (-0.00%)
Send messages: 10934879 -> 10934875 (-0.00%)
Cycle count: 30988230904 -> 30988228660 (-0.00%); split: -0.00%, +0.00%
Spill count: 534864 -> 534843 (-0.00%)
Fill count: 667081 -> 667068 (-0.00%)
Max live registers: 65686656 -> 65686624 (-0.00%)
Non SSA regs after NIR: 244185358 -> 244185335 (-0.00%)

Totals from 3 (0.00% of 704834) affected shaders:
Instrs: 4708 -> 4465 (-5.16%)
Send messages: 234 -> 230 (-1.71%)
Cycle count: 264382 -> 262138 (-0.85%); split: -0.88%, +0.03%
Spill count: 91 -> 70 (-23.08%)
Fill count: 73 -> 60 (-17.81%)
Max live registers: 647 -> 615 (-4.95%)
Non SSA regs after NIR: 3957 -> 3934 (-0.58%)

Tiger Lake
Totals:
Instrs: 230516919 -> 230515185 (-0.00%); split: -0.00%, +0.00%
Send messages: 12657684 -> 12657680 (-0.00%)
Cycle count: 23060318600 -> 23060279758 (-0.00%); split: -0.00%, +0.00%
Spill count: 548462 -> 548446 (-0.00%); split: -0.00%, +0.00%
Fill count: 582304 -> 582294 (-0.00%); split: -0.00%, +0.00%
Scratch Memory Size: 19538944 -> 19539968 (+0.01%)
Max live registers: 41713622 -> 41713593 (-0.00%)
Non SSA regs after NIR: 260667939 -> 260667712 (-0.00%); split: -0.00%, +0.00%

Totals from 174 (0.02% of 794323) affected shaders:
Instrs: 158346 -> 156612 (-1.10%); split: -1.13%, +0.04%
Send messages: 14330 -> 14326 (-0.03%)
Cycle count: 24859875 -> 24821033 (-0.16%); split: -0.32%, +0.16%
Spill count: 183 -> 167 (-8.74%); split: -9.29%, +0.55%
Fill count: 284 -> 274 (-3.52%); split: -7.39%, +3.87%
Scratch Memory Size: 9216 -> 10240 (+11.11%)
Max live registers: 12587 -> 12558 (-0.23%)
Non SSA regs after NIR: 164466 -> 164239 (-0.14%); split: -0.16%, +0.02%

Skylake
Totals:
Instrs: 158904982 -> 158903764 (-0.00%)
Send messages: 8490500 -> 8490496 (-0.00%)
Cycle count: 19732284279 -> 19732345496 (+0.00%); split: -0.00%, +0.00%
Spill count: 519127 -> 519115 (-0.00%)
Fill count: 594283 -> 594290 (+0.00%); split: -0.00%, +0.00%
Max live registers: 33708764 -> 33708739 (-0.00%)
Non SSA regs after NIR: 169377234 -> 169377007 (-0.00%); split: -0.00%, +0.00%

Totals from 174 (0.03% of 648725) affected shaders:
Instrs: 160391 -> 159173 (-0.76%)
Send messages: 14354 -> 14350 (-0.03%)
Cycle count: 24776486 -> 24837703 (+0.25%); split: -0.07%, +0.32%
Spill count: 332 -> 320 (-3.61%)
Fill count: 587 -> 594 (+1.19%); split: -0.17%, +1.36%
Max live registers: 12709 -> 12684 (-0.20%)
Non SSA regs after NIR: 166557 -> 166330 (-0.14%); split: -0.16%, +0.02%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32493>
 2024-12-05 21:39:07 +00:00
José Roberto de Souza
04bdbeec31 intel/dev/xe: Fix access to eu_per_dss_mask 
DRM_XE_TOPO_EU_PER_DSS and DRM_XE_TOPO_SIMD16_EU_PER_DSS can be any
number of bytes long but it was assuming it was always 4 bytes long.
That was not a issue because Xe KMD return 4 bytes even if only needs
1 or 2 bytes but that is a problem with our HW simulator that was
returning 2 bytes.

Fixes: a24d93aa89 ("intel/dev: Query and compute hardware topology for Xe")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32307>
 2024-12-05 20:30:44 +00:00
Lionel Landwerlin
371b7a9b0d anv: set pipeline flags correct for imported libs 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3d49cdb71e ("anv: implement VK_EXT_graphics_pipeline_library")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32507>
 2024-12-05 19:53:34 +00:00
Lionel Landwerlin
6e396b400a anv: fix missing bindings valid dynamic state change check 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9ddd296cd3 ("anv: implement VK_EXT_vertex_input_dynamic_state")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32507>
 2024-12-05 19:53:34 +00:00