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Author SHA1 Message Date
Emma Anholt fdf47acdc7 ci/freedreno: Flake the rest of the pbuffer/window dEQP-EGL tests. 
I had at least 3 of these in my logs, I see no reason not to fill out the
rest at this point.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12458>
 2021-08-18 22:47:12 +00:00
Emma Anholt 0d023aaaf5 ci/freedreno: Mark a new flaky SSBO length test. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12458>
 2021-08-18 22:47:12 +00:00
Ian Romanick 5ce3bfcdf3 intel/compiler: Lower 8-bit ops to 16-bit in NIR on all platforms 
This fixes the Crucible func.shader.shift.int8_t test on Gen8 and Gen9.
See https://gitlab.freedesktop.org/mesa/crucible/-/merge_requests/76.

With the previous optimizations in place, this change seems to improve
the quality of the generated code.  Comparing a couple Vulkan CTS tests
on Skylake had the following results.

dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:
SIMD8 shader: 36 instructions. 1 loops. 3822 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 27 instructions. 1 loops. 2742 cycles. 0:0 spills:fills, 5 sends

dEQP-VK.spirv_assembly.type.vec3.i8.max_frag:
SIMD8 shader: 39 instructions. 1 loops. 3922 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 37 instructions. 1 loops. 3682 cycles. 0:0 spills:fills, 5 sends

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Ian Romanick f0a8a9816a nir: intel/compiler: Add and use nir_op_pack_32_4x8_split 
A lot of CTS tests write a u8vec4 or an i8vec4 to an SSBO.  This results
in a lot of shifts and MOVs.  When that pattern can be recognized, the
individual 8-bit components can be packed much more efficiently.

v2: Rebase on b4369de27f ("nir/lower_packing: use
shader_instructions_pass")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Ian Romanick 89f639c0ca nir/algebraic: Remove spurious conversions from inside logic ops 
Not only does this eliminate a bunch of unnecessary type converting
MOVs, but it can also enable some SWAR.  The
dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag test does
something about like:

    c = a.x ^ b.x;
    d = a.y ^ b.y;
    e = a.z ^ b.z;

After this change, it looks more like:

    uint t = i8vec3AsUint(a) ^ i8vec3AsUint(b);
    c = extract_u8(t, 0);
    d = extract_u8(t, 1);
    e = extract_u8(t, 2);

On Ice Lake, this results in:

SIMD8 shader: 41 instructions. 1 loops. 3804 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 31 instructions. 1 loops. 2844 cycles. 0:0 spills:fills, 5 sends

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Ian Romanick 7c83aa0518 intel/fs: Emit better code for u2u of extract 
Emitting the instructions one by one results in two MOV instructions
that won't be propagated.  By handling both instructions at once, a
single MOV is emitted.  For example, on Ice Lake this helps
dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:

SIMD8 shader: 49 instructions. 1 loops. 4044 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 41 instructions. 1 loops. 3804 cycles. 0:0 spills:fills, 5 sends

Without "intel/fs: Allow copy propagation between MOVs of mixed sizes,"
the improvement is still 8 instructions, but there are more instructions
to begin with:

SIMD8 shader: 52 instructions. 1 loops. 4164 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 44 instructions. 1 loops. 3944 cycles. 0:0 spills:fills, 5 sends

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Ian Romanick e3f502e007 intel/fs: Allow copy propagation between MOVs of mixed sizes 
This eliminates some spurious, size-converting moves.  For example, on
Ice Lake this helps dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:

SIMD8 shader: 52 instructions. 1 loops. 4164 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 49 instructions. 1 loops. 4044 cycles. 0:0 spills:fills, 5 sends

Unfortunately, this doesn't clean everything up.  Here's a subset of the
"before" assembly:

send(8)         g11<1>UW        g2<0,1,0>UD     0x02106e02
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g7<4>UB         g11<8,8,1>UD                    { align1 1Q };
mov(8)          g12<1>UB        g7<32,8,4>UB                    { align1 1Q };
send(8)         g13<1>UW        g2<0,1,0>UD     0x02106e03
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g15<1>UW        g12<8,8,1>UB                    { align1 1Q };
mov(8)          g8<4>UB         g13<8,8,1>UD                    { align1 1Q };
mov(8)          g14<1>UB        g8<32,8,4>UB                    { align1 1Q };
mov(8)          g16<1>UW        g14<8,8,1>UB                    { align1 1Q };
xor(8)          g17<1>UW        g15<8,8,1>UW    g16<8,8,1>UW    { align1 1Q };

And here's the same subset of the "after" assembly:

send(8)         g11<1>UW        g2<0,1,0>UD     0x02106e02
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g7<4>UB         g11<8,8,1>UD                    { align1 1Q };
send(8)         g13<1>UW        g2<0,1,0>UD     0x02106e03
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g15<1>UW        g7<32,8,4>UB                    { align1 1Q };
mov(8)          g8<4>UB         g13<8,8,1>UD                    { align1 1Q };
mov(8)          g16<1>UW        g8<32,8,4>UB                    { align1 1Q };
xor(8)          g17<1>UW        g15<8,8,1>UW    g16<8,8,1>UW    { align1 1Q };

There are a lot of regioning and type restrictions in
fs_visitor::try_copy_propagate, and I'm a little nervious about messing
with them too much.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Ian Romanick a147717a93 nir/algebraic: Optimize some extract forms resulting from 8-bit lowering 
This eliminates some spurious, size-converting moves.  For example, on
Ice Lake this helps dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:

SIMD8 shader: 56 instructions. 1 loops. 4444 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 52 instructions. 1 loops. 4164 cycles. 0:0 spills:fills, 5 sends

v2: Condition two of the patterns on !options->lower_extract_byte.
Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Ian Romanick f9665040f1 intel/compiler: Document and assert some aspects of 8-bit integer lowering 
In the vec4 compiler, 8-bit types should never exist.

In the scalar compiler, 8-bit types should only ever be able to exist on
Gfx ver 8 and 9.

Some instructions are handled in non-obvious ways.

Hopefully this will save the next person some time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
 2021-08-18 22:03:37 +00:00
Adam Jackson fee4f7ef43 glx: Simplify context API profile computation 
GLX_ARB_create_context_profile has some clever language that sets the
default to core profile but silently degrades back to compat for pre-3.2
GLs. We can just do that, rather than track whether the user specified a
profile.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Adam Jackson a521b502b9 glx/dri: Collect the GLX context attributes in a struct 
dri2_convert_glx_attribs had way too many arguments, let's fix that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Adam Jackson 2cd0991def glx/drisw: Remove some misplaced error checks 
If the driver doesn't like these attributes it can reject them, it's not
libGL's job to verify them here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Adam Jackson 0d42033b26 glx/dri2: Require the driver to support v4 of __DRI_DRI2 
Mesa has supported this unconditionally since 10.1.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Adam Jackson bfad9e75c0 glx: Store the context vtable on the glx screen 
Again this is rewriting part of driX_create_context_attribs to be
caller-agnostic, so that we can eventually unify it among the DRI
backends.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Adam Jackson 145992890c glx: Fix and simplify the share context compatibility check 
We only end up with one DRI provider per screen, so the only way the
context vtable can differ is if they're not the same directness. Rewrite
the test in those terms to help us unify some of this code away in the
future. Also apply the same logic to the indirect context creation path.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Adam Jackson 5c71bf065f dri: Reformat DRI context attribute #defines 
These were confusingly sorted before.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>
 2021-08-18 21:11:02 +00:00
Mike Blumenkrantz 78c5cdf7e6 zink: clear current gfx/compute program upon unbinding its shaders 
this simplifies a lot of code

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12428>
 2021-08-18 20:58:36 +00:00
Mike Blumenkrantz c39cbd49c1 zink: do compute shader change on bind 
we can do this update earlier to optimize the actual compute path

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12428>
 2021-08-18 20:58:36 +00:00
Mike Blumenkrantz 26b5f4c45e zink: flag the gfx pipeline dirty and unset pipeline shader module on shader change 
there's no need to leave this until the module updating when the info
is known much earlier

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12428>
 2021-08-18 20:58:36 +00:00
Mike Blumenkrantz f676e6a64b zink: remove repeated lazy batch dd casts 
these all have an ergonomic cost

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12427>
 2021-08-18 20:46:24 +00:00
Mike Blumenkrantz 193ce77265 zink: remove redundant asserts from lazy descriptor set populate 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12427>
 2021-08-18 20:46:24 +00:00
Mike Blumenkrantz 96a6b8c808 zink: simplify get_descriptor_set_lazy params 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12427>
 2021-08-18 20:46:24 +00:00
Boyuan Zhang 35c3f5f08b radeon/vcn: check frame size change for vp9 header flags 
Beside show_frame and error_resilient_mode, also need to check if frame size
changes. FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS flag should be OFF if
frame size changes.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12368>
 2021-08-18 19:13:33 +00:00
Boyuan Zhang 0b6f8588a2 radeon/vcn: track width and height of the last frame 
Adding last width/height to keep tracking the size of the last frame.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12368>
 2021-08-18 19:13:33 +00:00
Boyuan Zhang 912d78d4f2 radeon/vcn: initilize num_temporal_layers for hevc 
Fixes: 51935d59

num_temporal_layers has not been initialized for hevc, which will cause hevc
encode failure.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12434>
 2021-08-18 18:06:21 +00:00
Jordan Justen 7faad66ab0 intel/pci-ids: Re-enable DG1 and add SG1 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11584>
 2021-08-18 17:35:41 +00:00
Sagar Ghuge 57bfd7122f anv: Fix VK_EXT_memory_budget to consider VRAM if available 
Instead of calling the OS query, re-run anv_update_meminfo to get the
latest from either the kernel memory info API or the OS as appropriate.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5173
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>
 2021-08-18 17:13:00 +00:00
Jason Ekstrand 758662759d anv: compute available memory in anv_init_meminfo 
We can now detect EXT_memory_budget support based on whether or not we
have non-zero available system memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>
 2021-08-18 17:13:00 +00:00
Jason Ekstrand 5c79c545e3 anv: Rework init_meminfo 
Instead of making LMEM the special case, unify the two paths by setting
up a fake drm_i915_query_memory_regions struct and filling it out based
on OS queries.  The important functional change here is that we now pass
system memory through the same GTT size and 3/4 filter that we were
using with the OS queries.  This should make behavior consistent on
integrated GPUs regardless of whether or not we have the memory region
query API.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>
 2021-08-18 17:13:00 +00:00
Jason Ekstrand be216ae9d9 anv: Move compute_heap_size lower in the file 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>
 2021-08-18 17:13:00 +00:00
Mike Blumenkrantz e0bd2fae8b softpipe: fix ci rule ordering to avoid unnecessarily running jobs 
fixes #5242

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12445>
 2021-08-18 14:11:42 +00:00
Mark Janes 09c1792d1f anv: warn if system memory is used 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12318>
 2021-08-18 13:55:14 +00:00
Mark Janes e610f4b5f2 anv: Allocate workaround buffer in local memory if present 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12318>
 2021-08-18 13:55:13 +00:00
Mark Janes 0afda06441 anv: Use local memory for block pool BO 
Allocating block pool BO into local memory means indirectly it allows us to
push our aux map table into local memory too.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12318>
 2021-08-18 13:55:13 +00:00
Mike Blumenkrantz 649251ad4e nir/lower_vectorize_tess_levels: set num_components for vectorized loads 
this otherwise explodes when rewriting e.g., a single array component load to a vec4

Fixes: f5adf27fb9 ("nir,radv: add and use nir_vectorize_tess_levels()")

fixes zmike/mesa#94

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12419>
 2021-08-18 12:18:15 +00:00
Erik Faye-Lund 45a61f1782 gallivm: fix texture-mapping with 16-bit result 
16bit integer support also implies using 16-bit results when sampling
textures.

Because we're returning the results in float SSA values instead of int,
we need to bitcast back to integers before truncating the values.

Fixes: 00ff60f799 ("gallivm: add 16-bit integer support")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12413>
 2021-08-18 07:55:34 +00:00
Mao, Marc fae1e99a15 iris: declare padding for iris_vue_prog_key 
Otherwise with some compilers/environments (Android) padding
may contain garbage and memcmp of the key will fail.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12438>
 2021-08-18 07:17:59 +00:00
Samuel Pitoiset b16f3261a7 radv: fix fast clearing depth images with mips on GFX10+ 
Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12325>
 2021-08-18 08:27:32 +02:00
Emma Anholt c94ff7dd81 freedreno/a5xx: Reduce packet emits for SSBO state. 
This is what I see happening in
dEQP-VK.spirv_assembly.instruction.compute.opatomic_storage_buffer.load on
pixel 2 (also where I found a buffer big enough to show how to encode the
size).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>
 2021-08-18 00:15:18 +00:00
Emma Anholt f10c7c4a5d freedreno/a5xx: Use ST4_ constants for SSBO/image state types. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>
 2021-08-18 00:15:18 +00:00
Eric Anholt 5b5dcbfe89 freedreno/a6xx: Skip setting up image dims constants. 
We just use resinfo anyway.  Notably, a6xx was only doing its setup in the
FS case and not CS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>
 2021-08-18 00:15:18 +00:00
Eric Anholt 994793c500 freedreno/ir3: Move a6xx's get_ssbo_size shl to NIR. 
Just cleaning up a TODO.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>
 2021-08-18 00:15:18 +00:00
Eric Anholt 547a2aa051 freedreno/ir3: Use the resinfo path for ssbo sizes on GL, too. 
Less state walking at draw time, in exchange for a SHL in the lookup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>
 2021-08-18 00:15:18 +00:00
Emma Anholt 513920ba82 freedreno/ir3: Only lower cube image sizes once. 
shader variants can cause ir3_nir_finalize() to run more than once, which
would make us keep dividing the size by 6.

Fixes: a48fc88571 ("freedreno/a6xx: Apply the cube image size lowering to GL, too.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>
 2021-08-18 00:15:18 +00:00
Rob Clark 89ab2a7b6f freedreno: Add a680 support 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12041>
 2021-08-17 23:24:23 +00:00
Jordan Justen cf23fbb040 meson: Check that bin/meson_get_version.py ran without an error 
According to https://mesonbuild.com/Reference-manual.html, the check
parameter is supported since meson 0.47.0.

This could have helped to catch the issue fixed by:

221871fb6d ("meson: Search for python3 before python for bin/meson_get_version.py")

as it would have caused the build to fail immediately.

It's still a good idea to check the result even though that issue is
now fixed.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12404>
 2021-08-17 15:18:03 -07:00
Icecream95 56ea259b42 panfrost: drm-shim support 
Reviewed-and-tested-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12431>
 2021-08-17 22:06:17 +00:00
Mike Blumenkrantz 8b810e545f zink: ci updates 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12423>
 2021-08-17 21:49:01 +00:00
Mike Blumenkrantz c1d342e986 zink: enable compat contexts 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12423>
 2021-08-17 21:49:01 +00:00
Jason Ekstrand 3ed4ddf076 anv,vulkan: Add a vk_image::wsi_legacy_scanout bit 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>
 2021-08-17 21:29:35 +00:00