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Author SHA1 Message Date
Eric Engestrom fbd644c59d meson: replace vk_wsi_args with dependencies to let meson take care of transitivity 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19497>
 2023-02-23 09:42:46 +00:00
Marcin Ślusarz 512126b26d intel/compiler: remove unused field from fs_thread_payload 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20957>
 2023-02-23 08:04:24 +00:00
Konstantin Seurer 6242fe3923 anv: Use vk_acceleration_structure 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21047>
 2023-02-22 11:58:57 +00:00
Marcin Ślusarz e29a964d02 intel/compiler/mesh: follow the type of offset variable 
This allows copy propagation to kick in, decreasing the overall
number of generated instructions.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21098>
 2023-02-21 11:10:24 +00:00
Marcin Ślusarz 15afb8dcc6 intel/compiler/mesh: apply URB payload mask once per program 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21098>
 2023-02-21 11:10:23 +00:00
Daniel Schürmann 2bb369dd8d nir: add assertions that loops don't have a Continue Construct 
Hoping that I didn't miss any, this *should* add assertions
to all functions and passes which explicitly handle 'nir_loop'.

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13962>
 2023-02-21 10:41:11 +00:00
Kenneth Graunke 96ba0344db intel: Use common helpers for TCS passthrough shaders 
Rob added these new helpers a while back, which freedreno and radeonsi
both share.  We should use them too.  The new helpers use variables and
system value intrinsics, so we can drop the explicit binding table
creation and just use the normal paths.

Because we have to rewrite the system value uploading anyway, we drop
the scrambling of the default tessellation levels on upload, and instead
let the compiler go ahead and remap components like any normal shader.
In theory, this results in more shuffling in the shader.  In practice,
we already do MOVs for message setup.  In the passthrough shaders I
looked at, this resulted in no extra instructions on Icelake (SIMD8
SINGLE_PATCH) and Tigerlake (8_PATCH).  On Haswell, one shader grew by
a single instruction for a pittance of cycles in a stage that isn't a
performance bottleneck anyway.  Avoiding remapping wasn't so much of an
optimization as just the way that I originally wrote it.  Not worth it.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20809>
 2023-02-20 03:54:24 +00:00
Emma Anholt 37b544e410 hasvk: Fix gfx8/9 VB range > 32bits workaround detection. 
Since the dirty range started out as 0..0, you would have 0..VBend as the
new dirty range on the first draw, and if your VB was >32b then you'd
flush every time you used it.  Instead, if there's no existing dirty range
then just set it to our new VB's range.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21370>
 2023-02-18 07:25:47 +00:00
Emma Anholt 4cd7976208 anv: Fix gfx8/9 VB range > 32bits workaround detection. 
Since the dirty range started out as 0..0, you would have 0..VBend as the
new dirty range on the first draw, and if your VB was >32b then you'd
flush every time you used it.  Instead, if there's no existing dirty range
then just set it to our new VB's range.

Perf results with zink+anv on my CFL:

sauerbraten:       +24.8182% +/- 0.602077% (n=5)
portal-2-v2.trace: +4.64289% +/- 0.285285% (n=5)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21370>
 2023-02-18 07:25:47 +00:00
Lionel Landwerlin 3b037ac073 anv: fix vma heap memory leak 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a5f9e59ce3 ("anv: Use vma_heap for descriptor pool host allocation")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21385>
 2023-02-17 21:37:34 +00:00
Lionel Landwerlin 18bf85468c anv: track vram only BOs to print things out on ENOMEM execbuf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21380>
 2023-02-17 13:45:00 +00:00
Lionel Landwerlin 0aa44b107a anv: move debug submit to helper and call it on execbuf failure 
Helps telling when you've run out of local memory.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21380>
 2023-02-17 13:45:00 +00:00
Tapani Pälli d53613dbd7 anv: Wa_14016407139, add required pc when SBA programmed 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21374>
 2023-02-17 12:44:00 +00:00
Lionel Landwerlin 14266d3c2d intel/perf: also add the oa timestamp shift on MTL 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 90c86fe63e ("intel: add MTL performance metrics")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21378>
 2023-02-17 12:10:05 +00:00
Faith Ekstrand d6248b8133 vulkan/layers: Use PUBLIC instead of VK_LAYER_EXPORT 
VK_LAYER_EXPORT is going away in the next Vulkan header update.  We
already have a PUBLIC macro in util/macros.h which does the same thing.
Unlike VK_LAYER_EXPORT, it should work in Windows too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21225>
 2023-02-17 03:42:34 +00:00
Faith Ekstrand f8aa83f0c8 intel/nir: Use nir_lower_mem_access_bit_sizes() 
This drops the Intel-specific pass in favor of the new generic one.

No shader-db changes on Skylake or DG2.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21232>
 2023-02-17 00:55:54 +00:00
Timothy Arceri 34e11963fa ci: enable dEQP-VK.ubo.random.all_shared_buffer.48 
The previous commits fix the slow compile time, allowing us to
enable this test.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5152

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20381>
 2023-02-16 23:31:59 +00:00
Emma Anholt ed62eec58b hasvk: Fix SPIR-V warning about TF unsupported on gen7. 
It's supported now.

Fixes: d82826ad44 ("anv: Implement VK_EXT_transform_feedback on Gen7")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21228>
 2023-02-16 18:11:44 +00:00
Emma Anholt 98455470ea hasvk: Silence conformance warning in CI. 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21228>
 2023-02-16 18:11:44 +00:00
Emma Anholt 570acf5655 ci: Add a manual full and 1/10th hasvk CTS runs. 
These are manual since they're on a runner in my basement that sometimes
can go down, but it'll be nice to have this for throwing the rare hasvk MR
at.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21228>
 2023-02-16 18:11:44 +00:00
José Roberto de Souza e050a00b9f intel/common: Move i915 files to i915 folder 
Following the organization done in intel/dev and intel/vulkan.

Probably due to some rebase issue we had a duplicated copyright header
in intel_gem_i915.h that is being removed in here too.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21256>
 2023-02-16 16:24:36 +00:00
Lionel Landwerlin 95d44a0773 hasvk: fix KHR_shader_float_controls reporting 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 13f68bcce1 ("hasvk: Tell spirv_to_nir float controls are always supported")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21349>
 2023-02-15 23:55:39 +00:00
José Roberto de Souza f331bab884 anv: Move execute_simple_batch() and queue_exec_locked() to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21255>
 2023-02-15 23:30:58 +00:00
José Roberto de Souza 0c8d8ae13c anv: Add gem_mmap to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21255>
 2023-02-15 23:30:58 +00:00
José Roberto de Souza 32a8250b46 anv: Add gem_close to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21255>
 2023-02-15 23:30:58 +00:00
Constantine Shablya 09501fe5a7 anv,hasvk: flush what UNIFORM_READ flushes on SHADER_READ 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8287
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21310>
 2023-02-15 19:53:41 +00:00
Erik Faye-Lund 29ffc79410 meson: don't pass vk wsi args where they don't belong 
Only code that cares about Vulkan WSI should get the corresponding
arguments passed. Otherwise, the Vulkan headers might end up including
other headers that we don't have the correct dependencies passed for.
So let's give those a dedicated variable, and only pass that where it's
actually needed.

Fixes: b39958a3a1 ("anv,nir: Move the ANV YCbCr lowering pass to common code")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8193
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21185>
 2023-02-15 18:35:14 +00:00
Constantine Shablya bd848ac92d hasvk: use Vulkan runtime's robust buffer access 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21338>
 2023-02-15 16:46:59 +00:00
Constantine Shablya 5053527806 anv: use Vulkan runtime's robust buffer access 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21338>
 2023-02-15 16:46:59 +00:00
Mark Janes 4b97e349cd intel: Implement Wa_16011448509 
"Use 3DSTATE_CONST command for individual shaders instead of
3DSTATE_CONST_ALL COMMAND"

On gen 12.0 platforms, 3DSTATE_CONSTANT_ALL command is not processed
correctly in certain cases.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21301>
 2023-02-15 01:10:42 +00:00
Lionel Landwerlin 9ac192d79d intel/fs: bound subgroup invocation read to dispatch size 
This is to avoid out of bound register accesses (potentially leading
to hangs) when the dispatch size is smaller than when is reported in
the NIR subgroup_size.

v2: Implement bounding with a mask (since workgroup sizes are powers of 2) (Faith)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 530de844ef ("intel,anv,iris,crocus: Drop subgroup size from the shader key")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21282>
 2023-02-14 21:29:42 +00:00
Rohan Garg d64000dbb3 anv/blorp: use existing function to convert the op to a string 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21283>
 2023-02-14 16:55:21 +00:00
Rohan Garg 80790f50db isl: fix some documentation 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21283>
 2023-02-14 16:55:21 +00:00
Rohan Garg 4e61191065 anv: reuse the VK_IMAGE_ASPECT_PLANES_BITS_ANV macro 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21283>
 2023-02-14 16:55:21 +00:00
Rohan Garg 5bb217a07a anv: drop unused headers 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21283>
 2023-02-14 16:55:21 +00:00
Michel Dänzer 53ce756eeb anv/grl: Use union for reinterpreting integer as float 
Fixes strict aliasing violations flagged by GCC 12:

../src/intel/vulkan/grl/include/GRLOCLCompatibility.h: In function ‘float as_float(uint32_t)’:
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h:182:13: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
  182 |     return *reinterpret_cast<float*>(&i);
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h: In function ‘float3 as_float3(int3)’:
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h:187:13: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
  187 |     return *reinterpret_cast<float3*>(&i3);
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h:187:13: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h: In function ‘float4 as_float4(int4)’:
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h:192:13: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
  192 |     return *reinterpret_cast<float4*>(&i4);
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/intel/vulkan/grl/include/GRLOCLCompatibility.h:192:13: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]

Fixes: 5f948503e4 ("anv: Import GRL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21236>
 2023-02-14 12:59:44 +00:00
Marcin Ślusarz 75e5d458a0 anv: enable task redistribution 
Disabling is no longer needed after "intel/compiler/mesh: use
slice id of task urb handles in mesh shaders".

This reverts commit 4eaecd7965.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7141

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21007>
 2023-02-14 09:36:53 +00:00
Marcin Ślusarz dd9bf86725 intel/compiler/mesh: use slice id of task urb handles in mesh shaders 
When mesh shader is spawned on a different slice than the originating
task shader, then input task urb handle can come from a different
slice, so masking this information off will load data from the current
slice, instead of the one where real data are.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21007>
 2023-02-14 09:36:53 +00:00
Lionel Landwerlin 9ddd296cd3 anv: implement VK_EXT_vertex_input_dynamic_state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21026>
 2023-02-14 09:05:35 +00:00
Lionel Landwerlin 95e3278285 anv: move 3DSTATE_VERTEX_ELEMENT emission to dynamic path 
Prep work for VK_EXT_vertex_input_dynamic_state

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21026>
 2023-02-14 09:05:35 +00:00
Lionel Landwerlin 46ecd56191 anv: remove copied information from runtime graphics state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21026>
 2023-02-14 09:05:35 +00:00
Marcin Ślusarz b1bb44cf65 anv: fix how unset gl_Viewport & gl_Layer are handled in mesh case 
See also: c6f69eea6a ("anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndex")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17620>
 2023-02-14 08:24:51 +00:00
Marcin Ślusarz 9d3e3c15f3 intel/compiler: replace gl_Layer & gl_ViewportIndex by 0 in fs if ms doesn't write it 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17620>
 2023-02-14 08:24:51 +00:00
Lionel Landwerlin eb5d7056e0 anv/hasvk: handle a SAMPLED_READ/STORAGE_READ access flags 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21277>
 2023-02-13 20:11:40 +00:00
Marcin Ślusarz 771f7c1d91 anv: bump ANV_MAX_QUEUE_FAMILIES 
Now it's possible to overflow anv_physical_device.queue.families
and anv_device.decoder.

CID: 1520852

Fixes: 056b0cb87f ("anv: add video engine support in various places")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21278>
 2023-02-13 12:19:45 +00:00
Lionel Landwerlin 295dd6f515 intel/dev: add a default urb value for intel_stub_gpu on dg2 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21249>
 2023-02-13 09:38:06 +00:00
Sviatoslav Peleshko 9b2ddd2c5e anv: Handle VkAccelerationStructureBuildRangeInfoKHR::transformOffset 
Previously it was not actually handled. This meant that all geometries
with the same transform buffer were using the same (first) transformation
matrix.

Fixes: f3ddfd81 ("anv: Build BVHs on the GPU with GRL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7575
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21227>
 2023-02-10 21:27:14 +00:00
Marcin Ślusarz 465c241266 intel/compiler/mesh: use U888X packed index format 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20910>
 2023-02-10 21:03:33 +00:00
Väinö Mäkelä 13f68bcce1 hasvk: Tell spirv_to_nir float controls are always supported 
This gets rid of the "Unsupported SPIR-V capability" warnings when
compiling shaders using float controls on gfx7.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
 2023-02-10 16:34:01 +00:00
Väinö Mäkelä 6f932276c3 hasvk: Don't claim shaderDenormPreserveFloat32 on gfx7 
From the Haswell PRM Vol. 7, "IEEE Floating Point Mode":
     "Single precision (F, Float) denorms are flushed to sign-preserved
      zero on input and output of any floating-point mathematical
      operation."

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
 2023-02-10 16:34:01 +00:00