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3361 Commits

Author SHA1 Message Date
Georg Lehmann
714a149396 nir: remove unsigned upper bound config 
All config information is now either in nir->info or nir->options.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
 2025-09-16 09:24:04 +00:00
Qiang Yu
310cfda034 ac/surface: add ac_compute_surface_modifier 
Used by radeonsi to export existing texture modifier.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
 2025-09-15 09:39:19 +00:00
Qiang Yu
98cd68ec05 ac/surface: add radeonsi exported modifiers to supported list 
radeonsi will export texture with these modifiers.

piglit tests:
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export-tex
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-tex-modifier

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
 2025-09-15 09:39:19 +00:00
Qiang Yu
1b0ec56c40 ac/surface: refine supported modifier list for multi block size 
Reference KMD convert_tiling_flags_to_modifier(). And we are
going to add 4K block size.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
 2025-09-15 09:39:19 +00:00
Georg Lehmann
76a502d75a ac/nir: set subgroup size for gs copy shader 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37294>
 2025-09-14 13:21:21 +00:00
David Rosca
070c3d2b89 ac/vcn: Add RADEON_VCN_IB_COMMON_OP_RESOLVEINPUTPARAMLAYOUT 
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37156>
 2025-09-08 10:52:05 +00:00
Georg Lehmann
83326af899 nir/builder: add nir_inverse_ballot_imm 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:56 +00:00
Georg Lehmann
ef8c364d3d nir: make inverse_ballot 1bit only 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
 2025-09-04 14:03:56 +00:00
David Rosca
2667db1114 radeonsi/vcn: Correctly set chroma location with EFC 
EFC supports horizontal left and vertical top/center.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36977>
 2025-09-01 10:30:38 +00:00
Marek Olšák
9e16ed7a13 ac/nir: switch nir_load_smem_amd uses to ac_nir_load_smem wrapper 
ac_nir_load_smem will use load_global_amd

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37101>
 2025-08-30 15:04:32 -04:00
Antonio Ospite
18ef7b82c6 radv: don't include amdgpu.h directly 
Don't include amdgpu.h directly in AMDGPU/RADV code, the only libdrm
pieces that are needed are handled in src/amd/common/ac_linux_drm.h
which already includes amdgpu.h

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36932>
 2025-08-28 18:08:20 +00:00
Georg Lehmann
13a9f27432 ac/nir: do not assume mesh cull flag is 1bit 
It will no longer be 1bit after a nir/lower_io bug is fixed.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36966>
 2025-08-27 08:46:33 +00:00
Arseny Kapoulkine
bb3727ce5a ac/rgp: Warn when RGP capture can't be saved without libelf 
Without this, mesa build on some distros may silently produce a version
of radv that silently refuses to save RGP traces

Signed-off-by: Arseny Kapoulkine <arseny.kapoulkine@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36960>
 2025-08-26 00:42:16 +00:00
Konstantin Seurer
9df7b48d2f nir: Use nir_def_as_* in more places 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36746>
 2025-08-24 14:03:09 +00:00
Yonggang Luo
9034a19aba radv: Fixes warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; 
../src/amd/vulkan/layers/radv_sqtt_layer.c(1040): error C2220: the following warning is treated as an error
../src/amd/vulkan/layers/radv_sqtt_layer.c(1040): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/layers/radv_sqtt_layer.c(1040): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings
../src/amd/vulkan/layers/radv_sqtt_layer.c(1052): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/layers/radv_sqtt_layer.c(1052): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings
../src/amd/vulkan/layers/radv_sqtt_layer.c(1059): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/layers/radv_sqtt_layer.c(1059): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings

../src/amd/vulkan/radv_dgc.c(2155): error C2220: the following warning is treated as an error
../src/amd/vulkan/radv_dgc.c(2155): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/radv_dgc.c(2155): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36862>
 2025-08-20 11:39:19 +00:00
Yonggang Luo
652e0d8ccf amdcommon: Use { 0 } initialize struct for .c files 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36862>
 2025-08-20 11:39:19 +00:00
David Rosca
231d877cc8 ac/vcn_dec: Add av1_intrabc_workaround 
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36725>
 2025-08-20 09:51:32 +00:00
Daniel Schürmann
52cd5f7e69 ac/nir_lower_mem_access_bit_sizes: Split unsupported shared memory instructions 
Totals from 1400 (1.75% of 79839) affected shaders: (Navi48)

MaxWaves: 38313 -> 38317 (+0.01%); split: +0.06%, -0.05%
Instrs: 1162521 -> 1199627 (+3.19%); split: -0.01%, +3.20%
CodeSize: 5874288 -> 6146832 (+4.64%); split: -0.01%, +4.65%
VGPRs: 79948 -> 79984 (+0.05%); split: -0.12%, +0.17%
Latency: 3703961 -> 3741457 (+1.01%); split: -0.02%, +1.04%
InvThroughput: 589594 -> 590597 (+0.17%); split: -0.06%, +0.23%
VClause: 22561 -> 22564 (+0.01%)
SClause: 19615 -> 19611 (-0.02%); split: -0.03%, +0.01%
Copies: 70721 -> 71678 (+1.35%); split: -0.25%, +1.60%
PreVGPRs: 61068 -> 61101 (+0.05%); split: -0.00%, +0.06%
VALU: 651754 -> 651785 (+0.00%); split: -0.07%, +0.07%
SALU: 141953 -> 141955 (+0.00%)
VOPD: 489 -> 485 (-0.82%); split: +0.41%, -1.23%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36133>
 2025-08-19 14:28:14 +00:00
Daniel Schürmann
63f7a03dd1 ac/nir: use HW-requirements on alignment for vectorizing LDS 
Totals from 663 (0.83% of 79839) affected shaders: (Navi48)

MaxWaves: 16758 -> 16752 (-0.04%)
Instrs: 748063 -> 750213 (+0.29%); split: -0.08%, +0.37%
CodeSize: 3864912 -> 3874984 (+0.26%); split: -0.11%, +0.37%
VGPRs: 40640 -> 40604 (-0.09%); split: -0.30%, +0.21%
Latency: 6977888 -> 6980523 (+0.04%); split: -0.05%, +0.09%
InvThroughput: 1176313 -> 1174557 (-0.15%); split: -0.23%, +0.08%
VClause: 13852 -> 13843 (-0.06%); split: -0.10%, +0.04%
SClause: 13221 -> 13219 (-0.02%)
Copies: 44814 -> 44760 (-0.12%); split: -0.41%, +0.29%
PreSGPRs: 29276 -> 29285 (+0.03%)
PreVGPRs: 30835 -> 30861 (+0.08%); split: -0.11%, +0.19%
VALU: 423942 -> 423782 (-0.04%); split: -0.21%, +0.17%
SALU: 81271 -> 81188 (-0.10%); split: -0.19%, +0.09%
VOPD: 243 -> 238 (-2.06%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36133>
 2025-08-19 14:28:14 +00:00
Georg Lehmann
9ed94371f7 amd: stop using custom gl_access_qualifier for access type 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36764>
 2025-08-15 08:26:10 +00:00
Georg Lehmann
f17cb6b714 amd: replace ACCESS_TYPE_SMEM with ACCESS_SMEM_AMD 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36764>
 2025-08-15 08:26:10 +00:00
Yinjie Yao
4cb6094f2e ac,radeonsi/vcn: Use correct swizzle_mode for vcn4 
On VCN4 SWIZZLE_MODE_8x8_1D_THIN_12_24BPP use different value
than previous VCN generations

Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36775>
 2025-08-14 17:24:40 +00:00
Samuel Pitoiset
a2d996b70c ac/descriptors: add a function to create a descriptor for HiZ surfaces 
HiZ is a separate image using standard image layout and tiling.
No need to support HiS which isn't available in any production chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
 2025-08-12 13:48:09 +00:00
Samuel Pitoiset
b2ea120732 ac,radv,radeonsi: fix programming PA_SU_PRIM_FILTER_CNTL on GFX12 
GFX12 seems to behave slightly differently. Setting these bits to TRUE
causes zero-area triangles to not pass the primitive clipping stage.
So, the actual number of primitives output by the primitive clipping
stage was wrong.

After digging a lot, it seems PAL doesn't set these bits either on
GFX12.

CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36670>
 2025-08-12 07:06:36 +00:00
Marek Olšák
d93156c2a2 ac: merge AC_ARG_INT & AC_ARG_FLOAT into single AC_ARG_VALUE 
nothing uses the type anymore

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36696>
 2025-08-11 15:32:30 -04:00
Marek Olšák
bb8d2e55d1 ac/llvm: make AC_ARG_FLOAT equal to AC_ARG_INT 
Nothing cares about the type anymore.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36696>
 2025-08-11 15:32:29 -04:00
Marek Olšák
54fe9aa664 ac: simplify AC_ARG_CONST_*PTR enums 
The pointer type doesn't matter anymore.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36696>
 2025-08-11 15:32:23 -04:00
David Rosca
d1165984e9 ac/vcn_dec: Add RDECODE_IT_SCALING_TABLE_SIZE 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
 2025-08-08 09:22:54 +00:00
Marek Olšák
900e56fc44 ac/nir: clarify the behavior of ac_nir_lower_ngg_options::can_cull 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36578>
 2025-08-07 18:12:53 +00:00
Marek Olšák
9244618e5f ac/nir/meta: allow compute blits with R5G6B5 & R5G5B5A1 formats on GFX9+ 
v2: add a workaround for incorrect hw rounding

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36578>
 2025-08-07 18:12:52 +00:00
Yonggang Luo
d83234c8f3 radv: Move the amdgpu.h defines for Win32 to ac_linux_drm.h 
This is for fixes compiling with MINGW/GCC

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36598>
 2025-08-07 07:47:42 +00:00
jglrxavpok
b987ec42ac radv: Avoid calls to strlen when parsing umr output to speed up hang progressing 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36451>
 2025-08-07 06:44:41 +00:00
Hans-Kristian Arntzen
d7b17d4d9c ac/nir: Avoid 0/0 when computing texel buffer size on Polaris. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13349
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36571>
 2025-08-06 10:37:50 +00:00
Samuel Pitoiset
1f490c836b ac/gpu_info,radv: use the maximum virtual address from the kernel 
Instead of hardcoding it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36573>
 2025-08-06 07:55:38 +02:00
Qiang Yu
196569b1a4 all: rename gl_shader_stage to mesa_shader_stage 
It's not only for GL, change to a generic name.

Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/\bgl_shader_stage\b/mesa_shader_stage/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
 2025-08-06 10:28:40 +08:00
Rhys Perry
cec845079e ac/nir/lower_ps: remove barrier for end_invocation_interlock 
SPIR-V->NIR now inserts this barrier itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36513>
 2025-08-04 09:30:06 +00:00
Alyssa Rosenzweig
82ae8b1d33 treewide: simplify nir_def_rewrite_uses_after 
Most of the time with nir_def_rewrite_uses_after, you want to rewrite after the
replacement. Make that the default thing to be more ergonomic and to drop
parent_instr uses.

We leave nir_def_rewrite_uses_after_instr defined if you really want the old
signature with an arbitrary after point.

Via Coccinelle patch:

    @@
    expression a, b;
    @@

    -nir_def_rewrite_uses_after(a, b, b->parent_instr)
    +nir_def_rewrite_uses_after_def(a, b)

Followed by a bunch of sed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
 2025-08-01 15:34:24 +00:00
Alyssa Rosenzweig
cc6e3b84cb treewide: use nir_def_as_* 
Via Coccinelle patch:

    @@
    expression definition;
    @@

    -nir_instr_as_alu(definition->parent_instr)
    +nir_def_as_alu(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_intrinsic(definition->parent_instr)
    +nir_def_as_intrinsic(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_phi(definition->parent_instr)
    +nir_def_as_phi(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_load_const(definition->parent_instr)
    +nir_def_as_load_const(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_deref(definition->parent_instr)
    +nir_def_as_deref(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_tex(definition->parent_instr)
    +nir_def_as_tex(definition)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
 2025-08-01 15:34:24 +00:00
Antonio Ospite
ddf2aa3a4d build: avoid redefining unreachable() which is standard in C23 
In the C23 standard unreachable() is now a predefined function-like
macro in <stddef.h>

See https://android.googlesource.com/platform/bionic/+/HEAD/docs/c23.md#is-now-a-predefined-function_like-macro-in

And this causes build errors when building for C23:

-----------------------------------------------------------------------
In file included from ../src/util/log.h:30,
                 from ../src/util/log.c:30:
../src/util/macros.h:123:9: warning: "unreachable" redefined
  123 | #define unreachable(str)    \
      |         ^~~~~~~~~~~
In file included from ../src/util/macros.h:31:
/usr/lib/gcc/x86_64-linux-gnu/14/include/stddef.h:456:9: note: this is the location of the previous definition
  456 | #define unreachable() (__builtin_unreachable ())
      |         ^~~~~~~~~~~
-----------------------------------------------------------------------

So don't redefine it with the same name, but use the name UNREACHABLE()
to also signify it's a macro.

Using a different name also makes sense because the behavior of the
macro was extending the one of __builtin_unreachable() anyway, and it
also had a different signature, accepting one argument, compared to the
standard unreachable() with no arguments.

This change improves the chances of building mesa with the C23 standard,
which for instance is the default in recent AOSP versions.

All the instances of the macro, including the definition, were updated
with the following command line:

  git grep -l '[^_]unreachable(' -- "src/**" | sort | uniq | \
  while read file; \
  do \
    sed -e 's/\([^_]\)unreachable(/\1UNREACHABLE(/g' -i "$file"; \
  done && \
  sed -e 's/#undef unreachable/#undef UNREACHABLE/g' -i src/intel/isl/isl_aux_info.c

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36437>
 2025-07-31 17:49:42 +00:00
Marek Olšák
688a639117 nir: add nir_tex_instr::can_speculate 
Set to true everywhere except:
- spirv_to_nir used by Vulkan
- bindless handles in GLSL
- some internal shaders and driver-specific code

Acked-by: Job Noorman <job@noorman.info>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36099>
 2025-07-24 18:41:38 +00:00
Samuel Pitoiset
081c7ec7b1 radv: emit PGM_HI_PS in the gfx preamble on GFX12 
It never changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36293>
 2025-07-24 11:03:27 +00:00
Marek Olšák
43f18f5615 ac/nir: mark all input loads as reorderable and speculatable (for LICM) 
These are only memory loads.

We could do the same for LDS loads, which are not truly speculatable
in merged shaders (can't be moved before the barrier), but that's fine
because LICM only moves code out of loops, which can't have barriers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950>
 2025-07-24 06:31:16 +00:00
Marek Olšák
a7291074c8 ac/nir: don't vectorize to 96-bit and 128-bit LDS loads (it's slower) 
LLVM also generates better code with this.
(-0.51% code size in 153 shaders, less SGPR spilling)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950>
 2025-07-24 06:31:16 +00:00
Marek Olšák
ac52e82868 ac/surface/gfx12: select 64K tiling for sparse MSAA textures 
addrlib doesn't do it automatically for MSAA

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950>
 2025-07-24 06:31:16 +00:00
Marek Olšák
8fb8bb6840 ac/surface/gfx12: add addr_from_coord for sparse MSAA textures 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35950>
 2025-07-24 06:31:16 +00:00
Georg Lehmann
d906fa041a ac/nir: don't lower 8/16bit bitfield_select 
This is just a bitwise operation, we can support all sizes.

No Foz-DB changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36141>
 2025-07-21 20:42:32 +00:00
Alyssa Rosenzweig
6b34e2174e nir: introduce ergonomic tex builder 
for intrinsics, we have these really nice builders using designated initializers
+ macros to specify optional indices. texture instrs have even more craziness
involved, but we can do the same trick. this commit takes the existing "fixed
form" deref-centric tex builders and generalizes them to work with non-deref
textures, making it useful also for GL and late VK passes, while providing an
API that strives to be ergonomic and consistent.

this series only implements a subset of possible texture operations for now, but
more generalizing could be added as people have need.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36050>
 2025-07-21 12:11:41 +00:00
David Rosca
e435ea78e8 ac/surface: Add ac_modifier_supports_video 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36192>
 2025-07-21 10:56:34 +00:00
Konstantin Seurer
df44b353ad radv: Optimize ray tracing position fetch 
Gets rid of a lot of indirection when fetching triangle positions.
Storing the primitive address increases register pressure by a bit but
the traversal shader which should have the highest register demand
should not be affected when position fetch is not used.

Totals:
Instrs: 4021686 -> 4022435 (+0.02%); split: -0.01%, +0.03%
CodeSize: 21235812 -> 21235832 (+0.00%); split: -0.02%, +0.02%
Latency: 23402275 -> 23412110 (+0.04%); split: -0.04%, +0.09%
InvThroughput: 4352818 -> 4352206 (-0.01%); split: -0.04%, +0.02%
VClause: 101906 -> 102058 (+0.15%); split: -0.03%, +0.18%
Copies: 342210 -> 342368 (+0.05%); split: -0.09%, +0.14%
Branches: 114988 -> 114993 (+0.00%)
PreVGPRs: 26551 -> 27111 (+2.11%)
VALU: 2249366 -> 2249524 (+0.01%); split: -0.01%, +0.02%
SALU: 529828 -> 529808 (-0.00%); split: -0.01%, +0.00%

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35533>
 2025-07-19 16:07:59 +00:00
Ruijing Dong
32a2012975 radeonsi/vcn: vcn5 av1 decoding context buffer fix 
In VCN5, the AV1 context buffer has changed to a bigger
one than VCN4. It fixed an AV1 decoding issue on VCN5.

Cc: mesa-stable

Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36208>
 2025-07-18 16:45:42 +00:00