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ac/nir/lower_ps: remove barrier for end_invocation_interlock

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SPIR-V->NIR now inserts this barrier itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36513>
This commit is contained in:
Rhys Perry
2025-08-01 10:34:05 +01:00
committed by Marge Bot
parent 4c36e08854
commit cec845079e
2 changed files with 1 additions and 23 deletions
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src/amd/common/nir/ac_nir_lower_ps_late.c
-23
View File
@@ -571,14 +571,6 @@ emit_ps_null_export(nir_builder *b, lower_ps_state *s)
!s->options->dcc_decompress_gfx11)
return;
/* The `done` export exits the POPS ordered section on GFX11+, make sure UniformMemory and
* ImageMemory (in SPIR-V terms) accesses from the ordered section may not be reordered below it.
*/
if (s->options->gfx_level >= GFX11 && pops)
nir_scoped_memory_barrier(b, SCOPE_QUEUE_FAMILY, NIR_MEMORY_RELEASE,
nir_var_image | nir_var_mem_ubo | nir_var_mem_ssbo |
nir_var_mem_global);
/* Gfx11 doesn't support null exports, and mrt0 should be exported instead. */
unsigned target = s->options->gfx_level >= GFX11 ?
V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL;
@@ -671,21 +663,6 @@ export_ps_outputs(nir_builder *b, lower_ps_state *s)
unsigned final_exp_flags = nir_intrinsic_flags(final_exp);
final_exp_flags |= AC_EXP_FLAG_DONE | AC_EXP_FLAG_VALID_MASK;
nir_intrinsic_set_flags(final_exp, final_exp_flags);
/* The `done` export exits the POPS ordered section on GFX11+, make sure UniformMemory and
* ImageMemory (in SPIR-V terms) accesses from the ordered section may not be reordered below
* it.
*/
if (s->options->gfx_level >= GFX11 &&
(b->shader->info.fs.sample_interlock_ordered ||
b->shader->info.fs.sample_interlock_unordered ||
b->shader->info.fs.pixel_interlock_ordered ||
b->shader->info.fs.pixel_interlock_unordered)) {
b->cursor = nir_before_instr(&final_exp->instr);
nir_scoped_memory_barrier(b, SCOPE_QUEUE_FAMILY, NIR_MEMORY_RELEASE,
nir_var_image | nir_var_mem_ubo | nir_var_mem_ssbo |
nir_var_mem_global);
}
} else {
emit_ps_null_export(b, s);
}
src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp
+1
View File
@@ -5136,6 +5136,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
break;
}
case nir_intrinsic_end_invocation_interlock: {
/* The `done` export exits the POPS ordered section on GFX11+. */
if (ctx->options->gfx_level < GFX11)
bld.pseudo(aco_opcode::p_pops_gfx9_ordered_section_done);
break;