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Author SHA1 Message Date
Rhys Perry fa4e08112e aco: remove SMEM constant/addition combining out of the loop 
There's no reason for this optimization to be in this loop.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13755>
 2021-12-17 22:14:36 +00:00
Rhys Perry dd18925f86 aco: skip &-4 before SMEM 
The hardware ignores the low 2 bits. I'm not sure if they are ignored
before or after the address is calculated, but this optimization should be
cautious enough.

fossil-db (Sienna Cichlid):
Totals from 259 (0.19% of 134572) affected shaders:
SpillSGPRs: 1381 -> 1382 (+0.07%)
SpillVGPRs: 1783 -> 1782 (-0.06%); split: -0.67%, +0.62%
CodeSize: 1598612 -> 1596084 (-0.16%); split: -0.30%, +0.14%
Scratch: 180224 -> 179200 (-0.57%); split: -1.14%, +0.57%
Instrs: 284885 -> 284268 (-0.22%); split: -0.34%, +0.12%
Latency: 6585634 -> 6603388 (+0.27%); split: -0.48%, +0.75%
InvThroughput: 2638983 -> 2648474 (+0.36%); split: -0.58%, +0.94%
VClause: 6797 -> 6820 (+0.34%); split: -0.15%, +0.49%
SClause: 6569 -> 6574 (+0.08%); split: -1.11%, +1.19%
Copies: 50561 -> 50586 (+0.05%); split: -0.61%, +0.66%
Branches: 10058 -> 10062 (+0.04%); split: -0.01%, +0.05%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13755>
 2021-12-17 22:14:36 +00:00
Rhys Perry cf5fc4b973 aco: disallow SMEM offsets that are not multiples of 4 
These can't be encoded on GFX6/7, and combining these additions causes
CTS failures on GFX10.3.

I think the low 2 MSBs are ignored before the addition, not after, so
load(a + 3, 0) becomes load(a, 3), which is the same as load(a, 0).

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13755>
 2021-12-17 22:14:36 +00:00
Bas Nieuwenhuizen 860532c5a1 radv: Add safety check for RGP traces on VanGogh. 
To avoid accidental hangs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13730>
 2021-12-17 21:25:01 +00:00
Emma Anholt 3077d96856 crocus: Clamp VS point sizes to the HW limits as required. 
Fixes piglit vs-point-size-zero.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14238>
 2021-12-17 19:41:54 +00:00
Emma Anholt 39ea803f9f ci/crocus: Add support for manual CI runs on my G41. 
Uses a shared runner at my house so we have an easy way to minimally test
crocus.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14238>
 2021-12-17 19:41:54 +00:00
Rhys Perry a65285f54b nir/opt_access: infer CAN_REORDER for global access 
fossil-db (Sienna Cichlid):
Totals from 352 (0.26% of 134621) affected shaders:
VGPRs: 17240 -> 17272 (+0.19%)
CodeSize: 1753640 -> 1755744 (+0.12%); split: -0.04%, +0.16%
Instrs: 323190 -> 323801 (+0.19%); split: -0.03%, +0.22%
Latency: 3241205 -> 3241293 (+0.00%); split: -0.10%, +0.10%
InvThroughput: 568927 -> 568067 (-0.15%); split: -0.16%, +0.00%
SClause: 12109 -> 10444 (-13.75%); split: -13.76%, +0.01%
Copies: 27802 -> 27717 (-0.31%); split: -0.56%, +0.26%
PreSGPRs: 14699 -> 14690 (-0.06%)
PreVGPRs: 15793 -> 15799 (+0.04%)

fossil-db (Polaris10):
Totals from 348 (0.26% of 135668) affected shaders:
SGPRs: 21446 -> 21574 (+0.60%); split: -0.15%, +0.75%
VGPRs: 17004 -> 16996 (-0.05%); split: -0.09%, +0.05%
CodeSize: 1782796 -> 1783060 (+0.01%); split: -0.03%, +0.05%
Instrs: 337828 -> 337921 (+0.03%); split: -0.03%, +0.06%
Latency: 3726328 -> 3726721 (+0.01%); split: -0.09%, +0.10%
InvThroughput: 1307917 -> 1299841 (-0.62%); split: -0.62%, +0.00%
VClause: 4327 -> 4337 (+0.23%); split: -0.09%, +0.32%
SClause: 12178 -> 10529 (-13.54%); split: -13.55%, +0.01%
Copies: 40227 -> 40244 (+0.04%); split: -0.19%, +0.24%
PreSGPRs: 14946 -> 14937 (-0.06%)
PreVGPRs: 15637 -> 15643 (+0.04%)

fossil-db (Pitcairn):
Totals from 351 (0.26% of 135668) affected shaders:
SGPRs: 20382 -> 20619 (+1.16%); split: -0.79%, +1.95%
CodeSize: 1789732 -> 1789836 (+0.01%); split: -0.04%, +0.04%
MaxWaves: 1947 -> 1949 (+0.10%)
Instrs: 352274 -> 352318 (+0.01%); split: -0.04%, +0.06%
Latency: 4057829 -> 4058226 (+0.01%); split: -0.08%, +0.09%
InvThroughput: 1332245 -> 1317578 (-1.10%); split: -1.11%, +0.01%
VClause: 8581 -> 8583 (+0.02%); split: -0.13%, +0.15%
SClause: 12187 -> 10552 (-13.42%); split: -13.43%, +0.02%
Copies: 44906 -> 44915 (+0.02%); split: -0.24%, +0.26%
PreSGPRs: 16571 -> 16562 (-0.05%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14227>
 2021-12-17 18:51:24 +00:00
Rhys Perry 403ae3b48e nir/algebraic: optimize more 64-bit imul with constant source 
Two 64-bit shifts and an addition are usually faster than the several
multiplications nir_lower_int64 creates.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14227>
 2021-12-17 18:51:24 +00:00
Rhys Perry c56cf157c5 nir/opt_load_store_vectorize: improve ssbo/global alias analysis 
If either the global access or the ssbo access is restrict, they shouldn't
alias.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14227>
 2021-12-17 18:51:24 +00:00
Samuel Pitoiset ac8afe3f44 radv: fix dynamic rendering global scissor 
Make sure to clamp the global scissor to the render area.

This fixes dEQP-VK.draw.dynamic_rendering.*oversized.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14170>
 2021-12-17 16:51:00 +00:00
Jason Ekstrand 288a670f17 anv/pipeline: Get rid of sample_shading_enable 
Putting it in the pipeline is a bit of a lie.  We no longer need it for
nir_lower_wpos_center. The only other user is pipeline_has_coarse_pixel
and that is used to build the shader key which we construct before we've
processed any NIR so we don't have accurate information at that time
anyway.  Instead, look at ms_info->sampleShadingEnable directly in
pipeline_has_coarse_pixel and trust the back-end to deal with disabling
coarse when we need per-sample dispatch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Jason Ekstrand deec7a590b anv,nir: Use sample_pos_or_center in lower_wpos_center 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Jason Ekstrand 3c89dbdbfe intel/fs: Implement the sample_pos_or_center system value 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Jason Ekstrand a580fd55e1 intel/fs: Rework emit_samplepos_setup() 
This rolls compute_sample_position into emit_samplepos_setup, its only
caller, by using a loop instead of calling it twice.  We also
early-return for the !persample_dispatch case instead of doing it as
part of the sample calculation.  This means that we don't call
fetch_payload_reg() to get sample_pos_reg unless we're actually going to
use it so the function is safe to call even if we haven't set up
sample_pos_reg.  This will be important for the next commit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Jason Ekstrand ac7255ed1e intel/fs: Return fs_reg directly from builtin setup helpers 
There's no good reason why we're allocating them on the heap and
returning a pointer.  Return the fs_reg directly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Jason Ekstrand e8acc5a7ea nir: Add a new sample_pos_or_center system value 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Jason Ekstrand 732b234ddb radeonsi/nir: Check for VARYING_SLOT_PRIMITIVE_ID not SYSTEM_VALUE 
This function is called on load/store_input/output.  It makes no sense
for it to get a SYSTEM_VALUE enum.  This only doesn't explode because
SYSTEM_VALUE_PRIMITIVE_ID happens to be below VARYING_SLOT_VAR0 so it
doesn't interact with any actual varyings.  The next commit is going to
add another system value which will push SYSTEM_VALUE_PRIMITIVE_ID up by
one so it will equal VARYING_SLOT_VAR0 and then the first FS input will
always get smashed to flat which isn't what we want.

Fixes: b59bb9c07a ("radeonsi: force flat for PrimID early in si_nir_scan_shader")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
 2021-12-17 16:02:16 +00:00
Pierre-Eric Pelloux-Prayer 41cc6a4c7f glthread: only log glthread destroy reason when it's not NULL 
Fixes: 670759a208 ("glthread: inline _mesa_glthread_restore_dispatch and merge disable & destroy")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14226>
 2021-12-17 11:56:24 +00:00
Pierre-Eric Pelloux-Prayer c1860a6848 radeonsi: don't use perp. end caps when line smoothing is on 
The line smoothing algorithm causes the diagonal line to be visible.

See: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700#note_1187405

Fixes: 4571778008 ("radeonsi: set PERPENDICULAR_ENDCAP_ENA for wide AA lines")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14226>
 2021-12-17 11:56:24 +00:00
Rhys Perry 94603786c5 aco: fix check_vop3_operands() for f16vec2 ffma fneg combine 
For v_pk_fma_f16, we should consider all three operands, not the first
two.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 15a375b4c8 ("radv,aco: don't lower some ffma instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14229>
 2021-12-17 11:16:12 +00:00
Marcin Ślusarz 504e5cb4e8 nir/print: print const value near each use of const ssa variable 
Without/with NIR_DEBUG=print,print_const:

-vec4 32 ssa_60 = fadd ssa_59, ssa_58
+vec4 32 ssa_60 = fadd ssa_59 /*(0xbf800000, 0x3e800000, 0x00000000, 0x3f800000) = (-1.000000, 0.250000, 0.000000, 1.000000)*/, ssa_58

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13880>
 2021-12-17 10:04:50 +00:00
Marcin Ślusarz 23f8f836e0 nir/print: group hex and float vectors together 
Vectors are much easier to follow in this format, because developer cares
either about hex or float values, never both.

Before/after:

-vec4 32 ssa_222 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */)
+vec4 32 ssa_222 = load_const (0x00000000, 0x00000000, 0x3f800000, 0x3f800000) = (0.000000, 0.000000, 1.000000, 1.000000)

-vec1 32 ssa_174 = load_const (0xbf800000 /* -1.000000 */)
+vec1 32 ssa_174 = load_const (0xbf800000 = -1.000000)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13880>
 2021-12-17 10:04:50 +00:00
Marcin Ślusarz d2b4051ea9 nir/print: move print_load_const_instr up 
... to avoid forward declarations in future commit

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13880>
 2021-12-17 10:04:50 +00:00
Juan A. Suarez Romero bc11dc7187 broadcom/ci: restructure expected results 
Sort/rename the files so expected tests are classified by device.

No need to split the tests by driver (e.g., V3D vs V3DV).

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13983>
 2021-12-17 09:15:34 +00:00
Bas Nieuwenhuizen ed7c48f94a radv/amdgpu: Only wait on queue_syncobj when needed. 
If signalled on the same queue it is totally useless, so only wait
if we have a syncobj that is explicitly being waited on, which can
be from potentially another queue/ctx. (Ideally we'd check but there
is no way to do so currently. Might revisit when we integrate the
common sync framework)

Fixes: 7675d066ca ("radv/amdgpu: Add support for submitting 0 commandbuffers.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14214>
 2021-12-17 08:54:08 +00:00
Jason Ekstrand 3878094eb1 anv: Drop anv_sync_create_for_bo 
The older helper is unused so we can roll it all into
anv_create_sync_for_memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
 2021-12-17 00:55:31 +00:00
Lionel Landwerlin b00086d393 anv,wsi: simplify WSI synchronization 
Rather than using 2 vfuncs, use one since we've unified the
synchronization framework in the runtime with a single vk_sync object.

v2 (Jason Ekstrand):
 - create_sync_for_memory is now in vk_device

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
 2021-12-17 00:55:31 +00:00
Jason Ekstrand 9ae1e621e5 anv: Implement vk_device::create_sync_for_memory 
Fixes: 36ea90a361 ("anv: Convert to the common sync and submit framework")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
 2021-12-17 00:55:31 +00:00
Jason Ekstrand 2188829d29 vulkan/queue: Handle WSI memory signal information 
We handle it by asking the driver to create a vk_sync that wraps a
VkDeviceMemory object and gets passed as one of the signal ops.

Fixes: 9bffd81f1c ("vulkan: Add common implementations of vkQueueSubmit and vkQueueWaitIdle")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
 2021-12-17 00:55:31 +00:00
Lionel Landwerlin cdf101455d vulkan: fix missing handling of WSI memory signal 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b996fa8efa ("anv: implement VK_KHR_synchronization2")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5744
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
 2021-12-17 00:55:31 +00:00
Ian Romanick ff44547ea4 intel/stub: Implement shell versions of DRM_I915_GEM_GET_TILING and DRM_I915_SEM_GET_TILING 
This is necessary to use intel_stub_gpu with Crocus.

v2: Remove unused i915_bo::swizzle_mode. Noticed by Emma.

Fixes: 953a4ca6fe ("intel: Add has_bit6_swizzle to devinfo")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14218>
 2021-12-16 23:06:38 +00:00
Ian Romanick 2dc7c24b80 intel/stub: Silence "initialized field overwritten" warning 
src/intel/tools/intel_noop_drm_shim.c:459:36: warning: initialized field overwritten [-Woverride-init]
  459 |    [DRM_I915_GEM_EXECBUFFER2_WR] = i915_ioctl_noop,
      |                                    ^~~~~~~~~~~~~~~

Fixes: 0f4f1d70bf ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14218>
 2021-12-16 23:06:38 +00:00
Emma Anholt 9c722a06ed ci/freedreno: Add known flakes from the last month. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14239>
 2021-12-16 22:37:53 +00:00
Adam Jackson c77e5af7a3 glx: Fix GLX_NV_float_buffer fbconfig handling 
Since we didn't record this attribute from the server, we wouldn't
account for it in glXChooseFBConfig, and glXGetFBConfigAttrib wouldn't
know about it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14221>
 2021-12-16 22:05:20 +00:00
Chia-I Wu 108881cbcc venus: add some trace points 
Add trace points for

 - vn_AcquireNextImage2KHR and vn_QueuePresentKHR
 - vn_AcquireImageANDROID and vn_QueueSignalReleaseImageANDROID
 - vn_BeginCommandBuffer and vn_EndCommandBuffer
 - vn_*Wait*
 - vn_Queue*
 - vn_instance_wait_roundtrip
 - shmem allocations and cache miss/skip

v2: fix cache miss/skip trace points (Ryan)

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org> (v1)
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14215>
 2021-12-16 19:27:56 +00:00
Michel Zou 631b3fe3e9 meson: correctly detect linker arguments 
Fixes: 22673a98 ("meson: Check arguments before adding")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13961>
 2021-12-16 17:19:28 +00:00
Emma Anholt 7a22967de3 r300: Remove unused RC_OPCODE_DPH 
Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt 9312bfb5fb r300: Remove unused RC_OPCODE_SFL 
Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt 495d119aa9 r300: Remove unused RC_OPCODE_CLAMP. 
Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt 9ed55c0c15 r300: Remove unused RC_OPCODE_SWZ. 
Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt a982d0baf3 r300: Remove unused RC_OPCODE_XPD. 
Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt 2e2b755ecb r300: Remove unused RC_OPCODE_ABS. 
Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt 7a0c3b1024 r300: Remove support for SCS. 
Nothing generates this meta-op in the backend, so we don't need it.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Emma Anholt acef6b6bb3 r300: Remove some dead compiler code. 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
 2021-12-16 16:57:02 +00:00
Marcin Ślusarz f7e63ec5d8 nir/print: compact printing of intrinsic indices 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14222>
 2021-12-16 09:43:13 +00:00
Marcin Ślusarz d8fa625bb3 nir/print: expand printing of io semantics.gs_streams 
gs_streams can be set for at least 2 other intrinsics.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14222>
 2021-12-16 09:43:13 +00:00
Marcin Ślusarz be25db9f0f nir/print: simplify printing of IO semantics 
Some of the tested flags are set for other intrinsics and they are
printed only when set, so there's no point in checking exact intrinsic
name or shader stage.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14222>
 2021-12-16 09:43:13 +00:00
Kenneth Graunke 7325179bcb intel/compiler: Use uppercase enum values in brw_ir_performance.cpp 
This is by far the more common style in Mesa.  It also gives a cue that
e.g. num_dependency_ids is a fixed definition rather than some kind of
local variable maintaining a count.

While hre, we also rename the enums to have full prefixes to prepare for
a future where we use them in multiple files for future backend work.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14182>
 2021-12-16 09:00:57 +00:00
Kenneth Graunke d3f4f23ca3 intel/vec4: Inline emit_texture and move helpers to brw_vec4_nir.cpp 
emit_texture() only has one caller, nir_emit_texture().  We may as well
inline that.  Move the associated helper functions for emitting sampler
messages there as well, to keep associated code nearby.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5183
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14191>
 2021-12-16 00:09:45 -08:00
Kenneth Graunke 92d194427d intel/vec4: Use nir_texop in emit_texture instead of translating 
We eliminated the GLSL IR -> vec4 backend ages ago, so the only caller
uses a nir_texop enum.  Drop a layer of translating.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14191>
 2021-12-16 00:09:44 -08:00