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intel/vec4: Use nir_texop in emit_texture instead of translating

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We eliminated the GLSL IR -> vec4 backend ages ago, so the only caller
uses a nir_texop enum.  Drop a layer of translating.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14191>
This commit is contained in:
Kenneth Graunke
2021-12-13 16:46:23 -08:00
parent 2729a741fc
commit 92d194427d
3 changed files with 22 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_vec4.h
+1 -1
View File
@@ -254,7 +254,7 @@ public:
void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
void emit_texture(ir_texture_opcode op,
void emit_texture(nir_texop op,
dst_reg dest,
int dest_components,
src_reg coordinate,
src/intel/compiler/brw_vec4_nir.cpp
+1 -28
View File
@@ -1944,31 +1944,6 @@ vec4_visitor::nir_emit_jump(nir_jump_instr *instr)
}
}
static enum ir_texture_opcode
ir_texture_opcode_for_nir_texop(nir_texop texop)
{
enum ir_texture_opcode op;
switch (texop) {
case nir_texop_lod: op = ir_lod; break;
case nir_texop_query_levels: op = ir_query_levels; break;
case nir_texop_texture_samples: op = ir_texture_samples; break;
case nir_texop_tex: op = ir_tex; break;
case nir_texop_tg4: op = ir_tg4; break;
case nir_texop_txb: op = ir_txb; break;
case nir_texop_txd: op = ir_txd; break;
case nir_texop_txf: op = ir_txf; break;
case nir_texop_txf_ms: op = ir_txf_ms; break;
case nir_texop_txl: op = ir_txl; break;
case nir_texop_txs: op = ir_txs; break;
case nir_texop_samples_identical: op = ir_samples_identical; break;
default:
unreachable("unknown texture opcode");
}
return op;
}
void
vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
{
@@ -2108,9 +2083,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
}
}
ir_texture_opcode op = ir_texture_opcode_for_nir_texop(instr->op);
emit_texture(op, dest, nir_tex_instr_dest_size(instr),
emit_texture(instr->op, dest, nir_tex_instr_dest_size(instr),
coordinate, instr->coord_components,
shadow_comparator,
lod, lod2, sample_index,
src/intel/compiler/brw_vec4_visitor.cpp
+20 -19
View File
@@ -826,7 +826,7 @@ vec4_visitor::is_high_sampler(src_reg sampler)
}
void
vec4_visitor::emit_texture(ir_texture_opcode op,
vec4_visitor::emit_texture(nir_texop op,
dst_reg dest,
int dest_components,
src_reg coordinate,
@@ -843,27 +843,28 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
{
enum opcode opcode;
switch (op) {
case ir_tex: opcode = SHADER_OPCODE_TXL; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
case ir_txd: opcode = SHADER_OPCODE_TXD; break;
case ir_txf: opcode = SHADER_OPCODE_TXF; break;
case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
case ir_txs: opcode = SHADER_OPCODE_TXS; break;
case ir_tg4: opcode = offset_value.file != BAD_FILE
? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break;
case ir_query_levels: opcode = SHADER_OPCODE_TXS; break;
case ir_texture_samples: opcode = SHADER_OPCODE_SAMPLEINFO; break;
case ir_txb:
unreachable("TXB is not valid for vertex shaders.");
case ir_lod:
unreachable("LOD is not valid for vertex shaders.");
case ir_samples_identical: {
case nir_texop_tex: opcode = SHADER_OPCODE_TXL; break;
case nir_texop_txl: opcode = SHADER_OPCODE_TXL; break;
case nir_texop_txd: opcode = SHADER_OPCODE_TXD; break;
case nir_texop_txf: opcode = SHADER_OPCODE_TXF; break;
case nir_texop_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
case nir_texop_txs: opcode = SHADER_OPCODE_TXS; break;
case nir_texop_query_levels: opcode = SHADER_OPCODE_TXS; break;
case nir_texop_texture_samples: opcode = SHADER_OPCODE_SAMPLEINFO; break;
case nir_texop_tg4:
opcode = offset_value.file != BAD_FILE ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4;
break;
case nir_texop_samples_identical: {
/* There are some challenges implementing this for vec4, and it seems
* unlikely to be used anyway. For now, just return false ways.
*/
emit(MOV(dest, brw_imm_ud(0u)));
return;
}
case nir_texop_txb:
case nir_texop_lod:
unreachable("Implicit LOD is only valid inside fragment shaders.");
default:
unreachable("Unrecognized tex op");
}
@@ -1019,17 +1020,17 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
/* fixup num layers (z) for cube arrays: hardware returns faces * layers;
* spec requires layers.
*/
if (op == ir_txs && devinfo->ver < 7) {
if (op == nir_texop_txs && devinfo->ver < 7) {
/* Gfx4-6 return 0 instead of 1 for single layer surfaces. */
emit_minmax(BRW_CONDITIONAL_GE, writemask(inst->dst, WRITEMASK_Z),
src_reg(inst->dst), brw_imm_d(1));
}
if (devinfo->ver == 6 && op == ir_tg4) {
if (devinfo->ver == 6 && op == nir_texop_tg4) {
emit_gfx6_gather_wa(key_tex->gfx6_gather_wa[surface], inst->dst);
}
if (op == ir_query_levels) {
if (op == nir_texop_query_levels) {
/* # levels is in .w */
src_reg swizzled(dest);
swizzled.swizzle = BRW_SWIZZLE4(SWIZZLE_W, SWIZZLE_W,