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Rohan Garg f3d99e3535 anv: introduce ANV_TIMESTAMP_REWRITE_INDIRECT_DISPATCH 
In order to rewrite timestamps for indirect dispatch's, instroduce a
ANV_TIMESTAMP_REWRITE_INDIRECT_DISPATCH that repacks the PostSync field
for a EXECUTE_INDIRECT_DISPATCH.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg 9dd49e7a63 anv: memcpy the thread dimentions only when they're on the CPU 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg d161e3c2e2 iris: Emit a EXECUTE_INDIRECT_DISPATCH when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DISPATCH that allows us to:

  * Skip issuing mi load/store instructions for indirect parameters

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg 580728564e anv: Emit a EXECUTE_INDIRECT_DISPATCH when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DISPATCH that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg 6d4f43f0d6 anv: Emit EXECUTE_INDIRECT_DRAW when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DRAW that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters
  * Skip doing the indirect draw unroll on the CPU side when the
    appropriate stride is passed

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg 7a9e82e82f genxml/12.5: Add the EXECUTE_INDIRECT_DISPATCH instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg 4229757309 genxml/12.5: Add the EXECUTE_INDIRECT_DRAW instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg 6e060d99ba intel/dev: Add a bit for when the HW can do a indirect draw/dispatch unroll 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg fa350862e9 anv: refactor kernel dispatch to use new common functions 
Refactor the function to use the new common functions introduced for
indirect dispatch previously.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg 51d2d9a665 anv: Refactor loading indirect parameters and filling IDD 
Refactor out loading the indirect parameters and filling the interface
descriptor data.

Reworks:
 * Jordan: Change anv to use get_interface_descriptor_data which
   returns the IDD struct rather than filling it.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Gert Wollny ac4b8aab21 r600/sfn: Fix usage of std::string constructor 
Fixes: f718ac6268 (r600/sfn: Add a basic nir shader backend)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26415>
 2023-11-30 16:42:43 +00:00
Gert Wollny eb25c7a4e2 r600/sfn: keep workgroup and invocation ID registers for whole shader 
For some reason one must not overwrite these values "too early", so
pin them for the whole shader.

Fixes: 79ca45 (r600/sfn: rewrite NIR backend)
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10004

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25846>
 2023-11-30 16:04:05 +00:00
Gert Wollny 5de814171b r600/sfn: Allow skipping backend shader optimization for a subset of shaders 
This comes in handy when debugging problems with the backend optimizer

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25846>
 2023-11-30 16:04:05 +00:00
Erik Faye-Lund 777c25255b panfrost: minify dimensions when converting modifiers 
When blitting resources, we need to specify the boxes in mip-level sized
coordinates. For the X and Y coordinates, missing this makes things
behave correctly, but only because we end up clipping away the excess
area.

However, for the Z coordinate of 3D textures, this will make us read
outside of the mip-chain during blitting, making us stumble and crash.

But let's fix what we do for all dimensions. And while we're at it,
rewrite the code a bit, so we don't end up computing any needless
values.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26077>
 2023-11-30 15:43:59 +00:00
José Roberto de Souza b27ca68143 intel/dev: Adjust prefetch_size values for Xe2 engines 
Xe2 follows MTL and has different prefetch sizes for different
types of engines.

BSpec: 60223
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26396>
 2023-11-30 14:54:04 +00:00
Boyuan Zhang 046cc51223 radeonsi/vcn: add new logic for hevc multi slices reflist 
For multi slices hevc decoding, use the newly defined buffer to handle
the case for multi slices ref pic list.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:34 -05:00
Boyuan Zhang d07517d19f radeonsi: add new interface to handle multi slice reflist 
Add new flag and buffer to handle multi slice reflist case for hevc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:31 -05:00
Boyuan Zhang ffdc83e9dd frontend/va: add support for multi slices reflist 
According to codec spec, hevc supports different reference picture lists
for multi slices case. For example, each slice can have it's own ref pic
list. Add this support to pipe, and modify both frontend/va and radeonsi
accordingly.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:28 -05:00
Boyuan Zhang 26237b9807 gallium/pipe: define hevc max slices number 
No logic change, just use define instead of hardcoded number to make
it more clear.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:25 -05:00
Eric Engestrom 02fe92c908 ci: disable opengl & gles in debian-vulkan build 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26369>
 2023-11-30 08:47:07 +00:00
Eric Engestrom 69ec13b303 bin/python-venv: detect python version change 
The venv only works for a specific python version; when updating python,
the venv needs to be regenerated.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26354>
 2023-11-30 08:39:17 +00:00
Faith Ekstrand 01d15d8a38 nak: Revert "nak: Handle non-DW-aligned UBO loads" 
This reverts commit 70c9fc66ffab8cb85b37c74b507201097e16da85.  We're now
handling non-DW-aligned UBO loads in NIR where we can handle it a bit
more completely, we don't need to carry the nak_from_nir code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26412>
 2023-11-30 05:05:00 +00:00
Faith Ekstrand 67e6ca1924 nak/nir: Handle CBuf alignment rules 
The NIR lowering is more complete and lets us properly handle 16-bit
loads which, weirdly, require a 4B alignment.

Fixes: bda208665f ("nak: Handle non-DW-aligned UBO loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26412>
 2023-11-30 05:05:00 +00:00
Timothy Arceri 57acffbba8 glsl: remove GLSL IR lower_named_interface_blocks() 
We now use a NIR based lowering pass instead.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26001>
 2023-11-30 03:45:08 +00:00
Timothy Arceri cdf0ed8960 glsl: use the nir based lower_named_interface_blocks() 
Because we are now doing the lowering in NIR we need to move the code
that sets the compact flag on some builtin vars out of the glsl to nir
pass.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26001>
 2023-11-30 03:45:07 +00:00
Timothy Arceri bedf504d38 glsl: add nir based lower_named_interface_blocks() 
This will be used in the following patch to replace the GLSL IR
version of this pass.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26001>
 2023-11-30 03:45:07 +00:00
Faith Ekstrand 5311d8713d nak: Implement scan/reduce on booleans 
We could use the lowering in nir_lower_subgroups for this but it's a lot
more complicated than we need and uses quad_any/all which we don't have.

Fixes: cca40086c6 ("nak: Lower scan/reduce in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26411>
 2023-11-30 02:50:25 +00:00
Eric Engestrom fc30a29bd6 docs/calendar: add 23.3.x releases 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26405>
 2023-11-29 21:05:45 +00:00
Eric Engestrom e2cd0ece86 docs: update calendar for 23.3.0 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26405>
 2023-11-29 21:05:45 +00:00
Yiwei Zhang 3475c8cc41 venus: scrub msaa sample mask only with valid msaa state 
No crash in dEQP-VK.api.pipeline.pipeline_invalid_pointers_unused_structs.graphics

Fixes: 417437c715 ("venus: pipeline fixes for VK_EXT_extended_dynamic_state3")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26404>
 2023-11-29 20:49:29 +00:00
Pierre-Eric Pelloux-Prayer b9f4e3c39b Revert "radeonsi: decrease PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS to 1024" 
This reverts commit 03353bd752.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10222
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26401>
 2023-11-29 19:33:48 +00:00
Sagar Ghuge 4ebad93c9c anv,hasvk: Use uint32_t for queue family indices 
Vulkan API uses uint32_t for the queue family indices.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26387>
 2023-11-29 19:07:17 +00:00
Bas Nieuwenhuizen 748b7f80ef radv: Move sparse binding into a dedicated queue. 
1) This better reflects the reality that we only have one timeline
   of sparse binding changes.

2) Allows making it a threaded queue from the start in prep of
   explicit sync stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen 00faefa08e radv: Remove the sparse binding queue from coherent images. 
Never access the image on the queue family, so no need.

(Technically not sure if this is needed for Vulkan, somewhat of
 a backstop in case apps do it)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Bas Nieuwenhuizen 6ff98f9313 radv: Add implementation of cmd buffers for a sparse binding queue. 
None of the commands are allowed on these ...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Alessandro Astone 4f48a140ac asahi: Use the compat version of qsort_r 
Not all platforms define qsort_r, util_qsort_r takes care of that.

CC: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25553>
 2023-11-29 17:01:09 +00:00
José Roberto de Souza c9e41f25a1 anv: Add heaps for Xe KMD in platforms without LLC 
As Xe KMD don't support WB + 0 way coherency, so this are the only two
memory types possible for integrated GPUs without LLC in Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza 1a0d3504d5 anv: Fill PAT fields in Xe KMD gem_create and vm_bind uAPIs 
Unlike i915, Xe KMD needs the cache parameter in gem_create
then during vm bind it request the PAT index that matches previous
parameter.
The PAT index selected could have more memory caracteristics that KMD
don't need to know.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza 99ae565af2 anv: Prepare anv_device_get_pat_entry() for discrete GPUs 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza eb18a92ef9 iris: Fill PAT fields in Xe KMD gem_create and vm_bind uAPIs 
Unlike i915, Xe KMD needs the cache parameter in gem_create
then during vm bind it request the PAT index that matches previous
parameter.
The PAT index selected could have more memory caracteristics that KMD
don't need to know.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza d26bd29ab4 iris: Prepare iris_heap_to_pat_entry() for discrete GPUs 
Xe KMD requires PAT information for discrete GPUs as well.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza 05b3967ddc intel: Enable has_set_pat_uapi for Xe 
Xe KMD requires that all platforms supported by it set PAT information.
This will be implemented in Iris and ANV in the next patches.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza 183fd14143 intel: Sync xe_drm.h 
Sync xe_drm.h with commit ebe27e42c0a2 ("drm/xe/uapi: support pat_index selection with vm_bind").

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza 500e037661 intel: Add PAT entries for gfx12 and newer 
Xe KMD requires PAT for all platforms so here adding PAT entries to
all platforms supported by Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza d491742d19 anv: Add support all possible cached and coherent memory types 
This changes allow us to support HOST_COHERENT, HOST_CACHED and
HOST_COHERENT + HOST_CACHED memory types for platforms that has
the PAT uAPI.

Be aware that Xe KMD will not be able to support cached only memory
types, anv_xe_physical_device_init_memory_types() will reflect that
but internal usage should not allocate
VK_MEMORY_PROPERTY_HOST_CACHED_BIT only memory, hence the assert
added.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
José Roberto de Souza 3baab9bb38 anv: Rename ANV_BO_ALLOC_SNOOPED to ANV_BO_ALLOC_HOST_CACHED_COHERENT 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
 2023-11-29 14:57:42 +00:00
Alyssa Rosenzweig d50d9eccad ac,radv,radeonsi: use common 1D texture lowering 
It was pulled from ac.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26397>
 2023-11-29 14:04:15 +00:00
Erik Faye-Lund ba2bbe21b4 ci: opt-out panfrost from clang-format 
In 0e481bf463 ("ci: Opt out asahi from clang-format"), Alyssa
recommended other drivers to follow suit. Since Panfrost originates from
Alyssa, and I doubt any other of the developers particularly cares too
much about this, let's follow her recommendation.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26062>
 2023-11-29 13:01:08 +00:00
Jan Beich 112093f9e2 intel: make CLOCK_BOOTTIME optional for non-Linux 
src/intel/common/xe/intel_gem.c:71:9: error: use of undeclared identifier 'CLOCK_BOOTTIME'
   case CLOCK_BOOTTIME:
        ^

Fixes: ae0df368a8 ("intel/common: Add intel_gem_read_correlate_cpu_gpu_timestamp()")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26392>
 2023-11-29 10:14:01 +00:00
Jan Beich 5c32c41f65 intel: make CLOCK_TAI optional for non-Linux 
src/intel/common/xe/intel_gem.c:72:9: error: use of undeclared identifier 'CLOCK_TAI'
   case CLOCK_TAI:
        ^

Fixes: ae0df368a8 ("intel/common: Add intel_gem_read_correlate_cpu_gpu_timestamp()")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26392>
 2023-11-29 10:14:01 +00:00