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Author SHA1 Message Date
Yiwei Zhang
e8f66ef197 llvmpipe: refactor dmabuf and opaque fd handling 
This change:
1. add new helpers to handle dmabuf alloc/import/free
2. use FREE to match with alloc macro
3. simplify opaque fd code path

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
4d0fbd1c67 llvmpipe: handle os_dupfd_cloexec failure 
Make it easy to debug fd leak or hitting open fd limit.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
1be7832f3e llvmpipe: handle mmap failure for lp_texture 
This makes debugging easier. Also assert that sparse binding is only
used with resource_create_unbacked.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
67d54fd5dc llvmpipe: support sparse resource with LLVMPIPE_MEMORY_FD_TYPE_DMABUF 
There's already the type, and there's no concurrent usage of fd and
dmabuf fd, so just drop it. This fixes sparse resource to work with
dmabuf external memory for lavapipe. In addition, this makes sparse
resource from venus on lavapipe to work with dmabuf backing.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
e0acc5c2b4 llvmpipe: misc fixes for sparse binding 
This change:
1. Move size validation within sparse binding, but not escape to
   non-sparse code path.
2. Error out if sparse is requested on unsupported platforms.

Fixes: d747c4a874 ("lavapipe: Implement sparse buffers and images")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
66414c6b70 llvmpipe: add a missing alloc error handling in fd import 
Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Suggested-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
3e07f57d4a llvmpipe: fix udmabuf mmap error check 
Upon failing to mmap, MAP_FAILED (void *)-1 is returned instead of NULL.

Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Yiwei Zhang
3a655c212b llvmpipe: zero is also a valid fd 
Fixes: a062544d3d ("llvmpipe: Use an anonymous file for memory allocations")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
 2025-11-05 08:26:39 +00:00
Samuel Pitoiset
a0d607bfdb radv,aco: wait for all VMEM loads when the prolog loads large 64-bit attributes 
Not the most optimal solution but 64-bit vertex attributes are rarely
used. Could still revisit if we find a real use case that matters.

This fixes recent VKCTS coverage:

dEQP-VK.pipeline.fast_linked_library.vertex_input.component_mismatch.r64g64b64.*_to_dvec2
dEQP-VK.pipeline.shader_object_.*.vertex_input.component_mismatch.r64g64b64.*_to_dvec2

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14243
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38237>
 2025-11-05 07:26:45 +00:00
Samuel Pitoiset
ba5bf81aa2 aco: fix reserving VGPRs for 64-bit attributes in VS prologs 
Otherwise the fetch index would be overwritten if the attribute format
is 64-bit and more than 2 components are loaded.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14242
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38237>
 2025-11-05 07:26:45 +00:00
Eric R. Smith
6f24dad00e panfrost: add 422 AFBC formats 
Most of the infrastructure was already in place for 8 bit (we just
had to add the AFBC mode to use). We also needed to add support for
the 10 bit format (X6R10X6G10_X6R10X6B10_UNORM). Note that this
10 bit format is only supported for AFBC, for linear we have to fall
back to the old multi-plane way of handling it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Eric R. Smith
417be4f77e dri: check modifier in dri_create_image_from_winsys 
When importing an image, check that the specific combination of
format plus modifier is supported, rather than just checking the
format. This will allow drivers to support some YUV formats in
special cases (specific modifiers, like AFBC for panfrost) while
also allowing us to fall back to generic multi-plane formats when
those modifier+format combinations are not supported by
hardware.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Eric R. Smith
b11f543c4e mesa: Add R16G16_R16B16_UNORM and related formats 
Including the 10 bit variant X6R10X6G10_X6R10X6B10_UNORM. Only the
RG_RB variants seem to have fourccs, so those are the only ones being
added for now, although they would, obviously, be easy to add).

These are used for Y210, Y212, and Y216 fourccs. In particular Y210
is interesting for panfrost, as it is the fourcc used to indicate a
10 bit single plane 4:2:2 encoded as AFBC (similar to how YUYV is
the canonical AFBC for 10 bit 4:2:0).

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Eric R. Smith
55735b6146 pan: Add 16 bit AFBC support (v10+ only) 
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Eric R. Smith
7a1ef0cf85 panfrost: update AFBC code to handle tiling for 64bpp formats 
We had assumed AFBC superblocks were always tiled in an 8x8 pattern,
but this is true only for 32bpp and lower formats; for larger formats
the pattern is 4x4. This isn't an issue yet, but will be when we
support R16G16B16A16 in AFBC.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Eric R. Smith
3303a04d4f panfrost: add explicit get_dmabuf_modifier_planes override 
This is required because otherwise dri2_get_modifier_num_planes will be
confused: dri2_get_mapping_by_fourcc gives the emulated 2 plane YUYV,
but panfrost itself supports a hardware single plane YUYV. This is
arguably a problem with dri2, but other drivers have implemented
dri2_get_modifier_num_planes so we may as well. It also gives us a
hook for supporting more exotic planar configurations, should that
be necessary in the future.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Eric R. Smith
09b5802f9f panvk: sanity check block size for unorm format 
panvk_meta_get_unorm_format_for_blk_size() requires a block size of 4
or less, but we didn't actually check for that before calling it. Fix
that, and also rename the function because what we actually care about
isn't whether it is a unorm format, but a blendable format.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
 2025-11-04 22:28:03 +00:00
Sagar Ghuge
43d98a3f1a anv: Use correct engine class for companion RCS 
Fixes: 6f138fe723 ("anv: avoid null pointer access in utrace copies on CCS")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38247>
 2025-11-04 21:39:23 +00:00
spencer-lunarg
17d8a5d8ae lavapipe: Remove trailing whitespace 
Signed-off-by: spencer-lunarg <spencer@lunarg.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38223>
 2025-11-04 21:20:47 +00:00
Felix DeGrood
faddb5d497 anv/pps: remove assert for double init 
pps initializes perf counter multiple times, once from
GpuDataSource::register_data_source and once from
GpuDataSource::OnSetup. This is fine, except we should replace
failing assert with skip on second call.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38224>
 2025-11-04 20:54:34 +00:00
Konstantin Seurer
b962063d72 nir: Remove nir_parallel_copy_instr 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
 2025-11-04 18:51:51 +00:00
Konstantin Seurer
3f3faa82b8 nir/from_ssa: Stop using nir_parallel_copy_instr 
nir_parallel_copy_instr can be emulated using an intrinsic for each
entry and an array of arrays that is used by the pass to remember which
copies belong together.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
 2025-11-04 18:51:50 +00:00
Konstantin Seurer
b20fd0ef48 nir: Remove parallel copy handling from rewrite_uses_to_load_reg 
Parallel copies are only created by nir_convert_from_ssa which does not
use the helper.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
 2025-11-04 18:51:50 +00:00
Ian Romanick
67a6fc0160 nir/opt_if: See through inot 
Consider

    if (!x) {
       if (x) {
          ...
       }
    }

The inner use of `x` must be false, but so far only instances of `!x`
would have been replaced with a constant. See through the `inot` to
replace instances of `x` as well.

shader-db:

Lunar Lake
total instructions in shared programs: 17205147 -> 17204908 (<.01%)
instructions in affected programs: 56037 -> 55798 (-0.43%)
helped: 79 / HURT: 79

total cycles in shared programs: 879847886 -> 879992944 (0.02%)
cycles in affected programs: 5244138 -> 5389196 (2.77%)
helped: 141 / HURT: 125

Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
total instructions in shared programs: 19968312 -> 19968069 (<.01%)
instructions in affected programs: 65698 -> 65455 (-0.37%)
helped: 88 / HURT: 104

total cycles in shared programs: 884331007 -> 884469865 (0.02%)
cycles in affected programs: 4839695 -> 4978553 (2.87%)
helped: 172 / HURT: 136

LOST:   3
GAINED: 0

Ice Lake, Skylake, and Broadwell had similar results. (Ice Lake shown)
total instructions in shared programs: 20809765 -> 20809473 (<.01%)
instructions in affected programs: 65976 -> 65684 (-0.44%)
helped: 89 / HURT: 102

total cycles in shared programs: 872466849 -> 872433762 (<.01%)
cycles in affected programs: 5452888 -> 5419801 (-0.61%)
helped: 157 / HURT: 133

total spills in shared programs: 4014 -> 4010 (-0.10%)
spills in affected programs: 30 -> 26 (-13.33%)
helped: 1 / HURT: 0

total fills in shared programs: 3769 -> 3765 (-0.11%)
fills in affected programs: 50 -> 46 (-8.00%)
helped: 1 / HURT: 0

LOST:   3
GAINED: 1

fossil-db:

All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 910122459 -> 910097570 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 40045664 -> 40046176 (+0.00%)
Send messages: 40724361 -> 40724036 (-0.00%)
Loop count: 970500 -> 970054 (-0.05%)
Cycle count: 105785543442 -> 105794147978 (+0.01%); split: -0.02%, +0.02%
Spill count: 3426093 -> 3426032 (-0.00%); split: -0.00%, +0.00%
Fill count: 6525296 -> 6525210 (-0.00%); split: -0.00%, +0.00%
Max live registers: 188561553 -> 188519064 (-0.02%); split: -0.02%, +0.00%
Max dispatch width: 47958304 -> 47958496 (+0.00%); split: +0.00%, -0.00%
Non SSA regs after NIR: 227303232 -> 227296055 (-0.00%); split: -0.00%, +0.00%

Totals from 15417 (0.78% of 1977988) affected shaders:
Instrs: 16984488 -> 16959599 (-0.15%); split: -0.20%, +0.05%
Subgroup size: 512 -> 1024 (+100.00%)
Send messages: 900193 -> 899868 (-0.04%)
Loop count: 23059 -> 22613 (-1.93%)
Cycle count: 1200149390 -> 1208753926 (+0.72%); split: -1.48%, +2.20%
Spill count: 25838 -> 25777 (-0.24%); split: -0.29%, +0.06%
Fill count: 43627 -> 43541 (-0.20%); split: -0.28%, +0.08%
Max live registers: 2550741 -> 2508252 (-1.67%); split: -1.75%, +0.08%
Max dispatch width: 296736 -> 296928 (+0.06%); split: +0.08%, -0.02%
Non SSA regs after NIR: 3264670 -> 3257493 (-0.22%); split: -0.25%, +0.03%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38196>
 2025-11-04 18:04:00 +00:00
Faith Ekstrand
27d9e4ec2a nvk: VK_EXT_shader_uniform_buffer_unsized_array 
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38230>
 2025-11-04 17:25:04 +00:00
Georg Lehmann
83e9ae2d5c radv: do not report wave32 in gl_SubgroupSize for Doom Dark Ages 
The shaders in question use:

(memory_load + (gl_SubgroupSize - 1)) & ~(gl_SubgroupSize - 1)

My guess is that this is supposed to be the subgroup size of whatever
produced the value, not the subgroup size in this shader.
And because in the consumer the workgroup size is 32, we use wave32.

Fixes: a2d3cbac2a ("radv: determine subgroup/wave size early")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14187

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38214>
 2025-11-04 16:52:13 +00:00
Yiwei Zhang
763d2418b8 panvk: fix sample shading of internal blend shader for MSAA 
Align with gallium side. When fixed-function blending is not available,
the internal blend shader is used. This is handled by a single ST_TILE
in the blend shader with the current sample ID, which requires sample
shading enablement.

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38129>
 2025-11-04 16:31:32 +00:00
David Rosca
00b8fad3d3 radeonsi/vcn: Fix creating context buffer on VCN5 
VCN5 needs the context buffer for AV1 encode and when pre-encode
is enabled.
Replace the check for dpb slots (which is always 0 on VCN5) with
check for first encoded frame.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14186
Fixes: a0324576aa ("radeonsi/vcn: Stop using rvid_buffer")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38072>
 2025-11-04 14:59:16 +00:00
Alyssa Rosenzweig
17355f716b treewide: use UTIL_DYNARRAY_INIT 
Instead of util_dynarray_init(&dynarray, NULL), just use
UTIL_DYNARRAY_INIT instead. This is more ergonomic.

Via Coccinelle patch:

    @@
    identifier dynarray;
    @@

    -struct util_dynarray dynarray = {0};
    -util_dynarray_init(&dynarray, NULL);
    +struct util_dynarray dynarray = UTIL_DYNARRAY_INIT;

    @@
    identifier dynarray;
    @@

    -struct util_dynarray dynarray;
    -util_dynarray_init(&dynarray, NULL);
    +struct util_dynarray dynarray = UTIL_DYNARRAY_INIT;

    @@
    expression dynarray;
    @@

    -util_dynarray_init(&(dynarray), NULL);
    +dynarray = UTIL_DYNARRAY_INIT;

    @@
    expression dynarray;
    @@

    -util_dynarray_init(dynarray, NULL);
    +(*dynarray) = UTIL_DYNARRAY_INIT;

Followed by sed:

    bash -c "find . -type f -exec sed -i -e 's/util_dynarray_init(&\(.*\), NULL)/\1 = UTIL_DYNARRAY_INIT/g' \{} \;"
    bash -c "find . -type f -exec sed -i -e 's/util_dynarray_init( &\(.*\), NULL )/\1 = UTIL_DYNARRAY_INIT/g' \{} \;"
    bash -c "find . -type f -exec sed -i -e 's/util_dynarray_init(\(.*\), NULL)/*\1 = UTIL_DYNARRAY_INIT/g' \{} \;"

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38189>
 2025-11-04 13:39:48 +00:00
Alyssa Rosenzweig
f6f23dfdd1 util: add UTIL_DYNARRAY_INIT sentinel 
We have the invariant that zero-initializing is legal but it's not
obvious in the source code, so add a sentinel value for it to make code
that uses it crystal clear.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38189>
 2025-11-04 13:39:48 +00:00
Lionel Landwerlin
6f138fe723 anv: avoid null pointer access in utrace copies on CCS 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3e0ad0176b ("anv: Emit state cache invalidation after every compute dispatch")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38235>
 2025-11-04 13:17:44 +00:00
Lionel Landwerlin
df5f92d114 u_trace: reserve chunk space before emitting copies 
Some implementations can emit tracepoints when copying u_trace
buffers. It's important to reserve the slots we want to copy into
before emitting the copies so that both processes don't clash with one
another.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38199>
 2025-11-04 12:49:04 +00:00
Danylo Piliaiev
2798ef7bfd vulkan: Always fill DS state for EXT_dynamic_rendering_unused_attachments 
If renderpass has D/S attachment, but pipeline has D/S as UNDEFINED,
D/S should be properly disabled for the pipeline. The easiest way is to
ensure that D/S state is valid when pipeline's D/S format is UNDEFINED.
So we always create VkPipelineDepthStencilStateCreateInfo.

CC: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37550>
 2025-11-04 12:03:11 +01:00
Georg Lehmann
22dc06798b aco/optimizer: never unfuse fma 
This shouldn't change anything in practice, and reducing precision
if precise isn't set is weird.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38183>
 2025-11-04 07:54:02 +00:00
Georg Lehmann
6610905b43 aco: allow v_fma_mix with denorms for gfx9 chips where it's fused 
Only unfused mad unconditionally flushes denorms.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38183>
 2025-11-04 07:54:02 +00:00
Georg Lehmann
75e7fb03a5 aco: fix v_mad_mix denorm behavior 
It also flushes fp32 denorms, just like v_mad_f32.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38183>
 2025-11-04 07:54:02 +00:00
Samuel Pitoiset
95b9801ad2 radv/sqtt: do not try to resize the SQTT buffer for per-submit captures 
Doesn't make sense to try that and it will fail later anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38188>
 2025-11-04 06:57:38 +00:00
Andy Hsu
be9e0f2f6a meson: Support intel tools on Android. 
Signed-off-by: Andy Hsu <hwandy@google.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38131>
 2025-11-04 06:18:19 +00:00
Tapani Pälli
ed34f91545 anv: implement autostrip disable for Wa_14024997852 
Note that currently autostrip is disabled globally with
Wa_14021490052 for some gfx versions and steppings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37975>
 2025-11-04 05:17:30 +00:00
Tapani Pälli
7d9cf48fd7 iris: implement autostrip disable for Wa_14024997852 
Note that currently autostrip is disabled globally with
Wa_14021490052 for some gfx versions and steppings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37975>
 2025-11-04 05:17:30 +00:00
Tapani Pälli
0ff1dd9e0c intel/genxml: add registers handling autostrip for gfx200 
These registers need to be whitelisted by kernel so that we can use
it to disable autostrip at will. This is about Wa_14024997852.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37975>
 2025-11-04 05:17:30 +00:00
Tapani Pälli
9a71dcde1b intel/dev: update mesa_defs.json from internal database 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37975>
 2025-11-04 05:17:30 +00:00
Ryan Houdek
455eb2c751 freedreno/fdl: Fix typo in tiled_to_linear_2cpp 
The non-aarch64 path was copying in the wrong direction.

Fixes: 7a5a33e0e3 ("freedreno/fdl: Add tiling/untiling implementation for a6xx/a7xx")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38226>
 2025-11-04 02:48:35 +00:00
stefan11111
37f1d19a68 glx: Add some NULL pointer checks 
This prevents mesa from segfaulting if GLX is working on some screens, but not all screens.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: stefan11111 <stefan11111@shitposting.expert>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38201>
 2025-11-04 00:21:19 +00:00
Mel Henning
041216e605 nak/opt_lop: Don't handle modifiers in dedup_srcs 
The handling in dedup_srcs was incorrect because it would apply the
modifier from srcs[i] to the LUT without removing the modifier from the
instruction. We can fix and simplify this code by removing all modifiers
before the dedup_srcs() call, which we were doing immediately after the
call anyway.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13966
Fixes: 66c9c40f68 ("nak: Handle modifiers in dedup_srcs() in opt_lop()")
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Reviewed-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38220>
 2025-11-03 22:46:11 +00:00
Mel Henning
4b1303e29d nak/nvdisasm_tests: Test plop3 
Reviewed-by: Seán de Búrca <sdeburca@fastmail.net>
Reviewed-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38220>
 2025-11-03 22:46:11 +00:00
Ryan Mckeever
f43e1fe603 people: update my name/email 
Signed-off-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38225>
 2025-11-03 22:08:48 +00:00
Ryan Mckeever
dac4322b47 mailmap: update my name and email 
Signed-off-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38225>
 2025-11-03 22:08:48 +00:00
Lionel Landwerlin
53834ccb6a brw: disable io_semantic validation for mesh intrinsics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2f6b4803ab ("nir/validate: expand IO intrinsic validation with nir_io_semantics")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38222>
 2025-11-03 21:28:22 +00:00
Dylan Baker
74018f41ab anv: try to help coverity understand we're not racing 
Coverity notices that in this case part of the decision to go down the
locked path invovles reading a flag, which is turn set inside the
protected code. Additional threads can decide they need to go down the
locked path, and then wait on the lock, even though the first thread
willse the device_registered to true, which would have otherwise
prevented them from going down the locked path.

What Coverity doesn't know, is that it is a violation of the Vulkan API
contract to call this function from two different threads, so in
practice that cann't happen. We'll move the setting of the
image_device_registered out of the locked area to see if that pacifies
Coverity, and if not then we'll just ignore it.

CID: 1662067
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37582>
 2025-11-03 20:00:31 +00:00