radv,aco: wait for all VMEM loads when the prolog loads large 64-bit attributes
Not the most optimal solution but 64-bit vertex attributes are rarely used. Could still revisit if we find a real use case that matters. This fixes recent VKCTS coverage: dEQP-VK.pipeline.fast_linked_library.vertex_input.component_mismatch.r64g64b64.*_to_dvec2 dEQP-VK.pipeline.shader_object_.*.vertex_input.component_mismatch.r64g64b64.*_to_dvec2 Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14243 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38237>
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@@ -643,6 +643,14 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh
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continue_pc = Operand(prolog_input, s2);
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}
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/* Wait for all pending VMEM loads when the prolog loads large 64-bit
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* attributes because the vertex shader isn't required to consume all of
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* them and they might be overwritten. This isn't the most optimal solution
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* but 64-bit vertex attributes are rarely used.
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*/
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if (is_last_attr_large)
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wait_for_vmem_loads(bld);
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bld.sop1(aco_opcode::s_setpc_b64, continue_pc);
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program->config->float_mode = program->blocks[0].fp_mode.val;
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@@ -191,6 +191,11 @@ declare_vs_input_vgprs(enum amd_gfx_level gfx_level, const struct radv_shader_in
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unsigned num_attributes = util_last_bit(info->vs.input_slot_usage_mask);
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for (unsigned i = 0; i < num_attributes; i++) {
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ac_add_arg(&args->ac, AC_ARG_VGPR, 4, AC_ARG_VALUE, &args->vs_inputs[i]);
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/* The vertex shader isn't required to consume all components that are loaded by the prolog
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* and it's possible that more VGPRs are written. This specific case is handled at the end
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* of the prolog which waits for all pending VMEM loads if needed.
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*/
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args->ac.args[args->vs_inputs[i].arg_index].pending_vmem = true;
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}
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}
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