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Author SHA1 Message Date
Rob Clark
e6b2785811 freedreno/drm/virtio: Use userspace IOVA allocation 
If supported by host virglrenderer and host kernel, use userspace
allocated GPU virtual addresses.  This lets us avoid stalling on
waiting for response from host kernel until we need to know the
host handle (which is usually not until submit time).

Handling the async response from host to get host_handle is done
thru the submit_queue, so that in the submit path (hot) we do not
need any additional synchronization to know that the host_handle
is valid.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Rob Clark
ae01c27ac0 freedreno/drm/virtio: Support ring_idx 
ring_idx zero is the CPU ring, others map to the priority level, as each
priority level for a given drm_file on the host kernel side maps to a
single fence timeline.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Rob Clark
122cedf98c freedreno/drm: Move bo common init 
We'll need this to happen before virtio_bo_new() returns in the next
patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Rob Clark
d52455a962 freedreno/drm: Close bo handle after bo->destroy() 
For userspace allocated iova, we want to give the backend a chance to
release the iova before the handle is closed.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Rob Clark
4ed346c6fb freedreno/drm: Drop FD_PP_PGTABLE 
Unused.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Rob Clark
0004cae638 freedreno/drm/virtio: Appease valgrind 
Valgrind isn't seeing that the kernel is initializing the caps (or
returning an error).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Rob Clark
d79c71c705 freedreno: Misc indent fixes 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16086>
 2022-04-27 23:10:00 +00:00
Adam Jackson
c865416f44 glx/kopper: Wire up a way for SwapBuffers to fail 
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
0394f35424 zink/kopper: add a mechanism for checking swapchain status 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
4af98df955 zink: flag swapchain resources as swapchains 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
625457caaf zink: handle swapchain acquire failures more directly 
if acquire fails, the pending operation cannot be completed, so just
drop it

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
494d02eacf zink: fix return for zink_kopper_acquire 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
ce9cbeee33 zink: rework swapchain object check for acquires 
this is more accurate

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
a2c9cc7200 zink: unset image layout when killing swapchain 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
5cb9e5db72 zink: handle dead swapchains in acquire 
this is a no-op failure

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
651b71a6ca zink: flag swapchains when updating fails 
these are dead, they just don't know it yet

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Mike Blumenkrantz
b86c814347 zink: add a util function for finding swapchain resource 
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16038>
 2022-04-27 21:50:16 +00:00
Charmaine Lee
8d73315bce draw: fix double free of NIR IR 
Check the shader IR type first before freeing the NIR IR in
draw_delete_xxx_shader() in case the IR has been converted to TGSI
and the NIR IR has already been freed.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16199>
 2022-04-27 21:01:54 +00:00
Lionel Landwerlin
f4f350a06c anv: reemit 3DSTATE_STREAMOUT after memcpy 
This doesn't fix anything because memcpy is only used before secondary
buffer execution and we dirty everything after that.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16189>
 2022-04-27 18:43:00 +00:00
Sathishkumar S
f17d3a1251 radeon/vcn: skip create and destroy message for jpeg 
JPEG does not require create and destroy codec messages.
It is not firmware based, so these messages are redundant.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16160>
 2022-04-27 17:13:36 +00:00
Mike Blumenkrantz
de3890daa5 zink: add supported present modes to kopper displaytarget 
for use later

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16193>
 2022-04-27 16:52:25 +00:00
Cristian Ciocaltea
d89b95b247 ci: Limit Intel CPU scaling frequency for performance tests 
As an additional measure to mitigate thermal throttling, set the upper
limit for the CPU scaling frequency to 65% of maximum allowed by the
hardware.

The impact on the overall tests duration should be minimal since the
performance tests do not really put high load on the CPU.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16164>
 2022-04-27 18:46:05 +03:00
Cristian Ciocaltea
99b04cbb73 ci: Add CPU frequency adjustment capability 
Update intel-gpu-freq.sh script to offer the possibility to adjust CPU
operating frequencies in addition to GPU.

Note this is currently limited to just setting the maximum scaling
frequency as percentage of the maximum frequency allowed by the
hardware.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16164>
 2022-04-27 18:46:05 +03:00
Icecream95
76cea8e27b panfrost: Fix pack_32_2x16 implementation 
Fixes: 6f0eff548c ("pan/bi: Implement packing ops between 32-bit vec1 and 16-bit vec2")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16181>
 2022-04-27 15:30:09 +00:00
Samuel Pitoiset
92e5eee39e radv: use correct push constants range for internal operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16131>
 2022-04-27 15:08:59 +00:00
Juan A. Suarez Romero
031bcf686b v3d/simulator: add support for AMD cards 
Dumb buffers do not work with AMD gpus. So use AMD ioctl to create
proper buffers.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16187>
 2022-04-27 14:42:23 +00:00
Juan A. Suarez Romero
9c3144d2ef v3dv: store device_id on device init 
Instead of calling later an ioctl to get the device id, let's store it
while initializing the physical device.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16187>
 2022-04-27 14:42:23 +00:00
Jason Ekstrand
3f824e0e85 panvk: Eliminate unused vertex attributes 
We use nir_assign_io_var_locations() which compacts the varyings and
eliminates any unused input slots.  We need to do the same thing when
processing pVertexAttributeDescriptions[] or else we'll end up with
mismatches between the shader and the state setup code.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16183>
 2022-04-27 14:18:25 +00:00
Jason Ekstrand
e248c64f06 panvk: Take buffer offsets into account in BindVertexBuffers 
Found by inspection.  No idea what all it fixes.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16183>
 2022-04-27 14:18:25 +00:00
David Heidelberg
657b0ff861 ci/iris: Enable SKQP on Tiger Lake boards 
- SKQP gets included now in all amd64 LAVA builds.
 - add test job for Tiger Lake (tgl)
 - add manual test job for Whiskey Lake (whl), because all runners are
   already used
 - document that we have 13 tgl machines

Tests failed (on tgl):
 - gl_simpleaaclip_aaclip, 1 pixel off : https://okias.pages.freedesktop.org/-/mesa/-/jobs/21790629/artifacts///results/gl/report.html

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16048>
 2022-04-27 12:35:13 +00:00
David Heidelberg
c1e59bea05 ci: intel: Merge anv and iris into src/intel/ci 
This commit make simple adding tests which use both GL(ES) and VK.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16048>
 2022-04-27 12:35:13 +00:00
Erik Faye-Lund
3620e7e71c vulkan: drop empty vulkan_wsi_args 
This is always empty, so let's just get rid of it.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16162>
 2022-04-27 11:51:26 +00:00
Erik Faye-Lund
6623f60c34 vulkan: use c_msvc_compat_args for shared code 
Due to both Lavapipe on Windows and Dozen, we need to support MSVC in
the shared Vulkan code. So let's make sure we compile with the
compatibility flags for it.

Techinically speaking, we also need this in the wsi subdir, because we
also compile wsi_common_win32.c with MSVC. But wsi_common_wayland.c
contains void-pointer arithmetic, causing compiler errors if we do.

Fixing that properly is a bit more involved, because Meson doesn't love
passing different compiler arguments per source-file. The alternative is
to remove the void-pointer arithmetic, but that seems a bit pointless as
this code will never be compiled on MSVC.

So, let's leave that one out for now. We can probably do better in the
future, but this gets us a step further.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6386
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16162>
 2022-04-27 11:51:26 +00:00
Samuel Pitoiset
e6bcdc763c radv: enable radv_disable_sinking_load_input_fs for Grid Autosport 
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4228
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16165>
 2022-04-27 13:00:38 +02:00
Samuel Pitoiset
1dbfd2be4b radv: allow to disable sinking of load inputs for FS via drirc 
To workaround game bugs where partial derivatives are used in
non-uniform control flow. A proper solution needs to be implemented,
but as a quick fix disabling nir_opt_sink() works.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16165>
 2022-04-27 13:00:36 +02:00
Lucas Stach
6261ca7425 etnaviv: add tile size helper 
On older GPUs a color tile was always 64 Byte. On new GPUs with
CACHE128B256BPERLINE support the tile size is either 128 Byte or
256 Byte depending on the TS mode. Add a helper to return the
color tile size and use in in places that use hard-coded tile
size values or do their own calculation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
2d2f9572c2 etnaviv: use feature bit to check for big tile support 
128B/256B tile support is not a HALTI5 property, but has its own
separate feature bit.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
4122011697 etnaviv: properly set additional DEC400 compression states 
With access to HALTI5 GPUs with and without DEC400 compression it's
obvious that the previous compression state setup only worked when
DEC400 was present. Properly set up the compression state bits.

This is only the second part of the fix, first part is moving the
compression state to the correct bit location, which has already
happened via the import of new rnndb headers.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
17d9b0808a etnaviv: add support for big tile RS states 
On GPUs with the CACHE128B256BPERLINE feature the RS gained some
new state bits to deal with the new additional information required
for this big tile support.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
c2a3236d1a etnaviv: clean up tiling setup in etna_compile_rs_state 
Using the raw layout bits in the tiling setup makes this function harder
to read than necessary. Use the tiling bit defines and assign them to
some local bools with a proper name to make this easier to read.

No functional change.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
8d6b6e31e1 etnaviv: use feature bit for one const src per instuction limitation 
Support for multiple constant sources per instruction is not a HALTI5
capability, there is a separate feature bit to signal the availability
of this shader core enhancement.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
5fcf55bb15 etnaviv: use feature flag to determine which RS states to use 
We used the number of pipes to determine which state registers to use
for the RS pipe address configuration, as the dual pipe GPUs were the
first one where the new states were used. This isn't correct though,
as now there are single pipe GPUs which also use the new state
addresses.
There actually is a feature flag telling us to use the new RS pipe
address states, use it. As this feature flag is not available on early
GPUs using the new base address (mostly because we don't have HWDB
entries for them), still check for more than a single pipe as an
additional clue to use new states.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
7c46a48836 etnaviv: use new PE pipe address states on >= HALTI0 
We used the number of pipes to determine which state registers to use
for the PE pipe address configuration, as the dual pipe GPUs were the
first one where those new states were used. Now there are some new
single pipe GPUs where this logic breaks. HALTI0 added the new PE
address states and all GPUs with at least this feature level are using
the new states exclusively, even if they only have a single PE pipe.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
617339ab5b etnaviv: correct bits per tile and clear value for HALTI5 
Bits per tile and the tile clear value are not determined by the
HALTI version, but by two separate feature bits that are not always
present on HALTI5 GPUs. With big 128B/256B tile support the bits
per tile are always 4.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
dd8a314d3f etnaviv: update headers from rnndb 
Update to rnndb commit ad665b720421.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
8c153bb091 etnaviv: fill all minor GPU features from the kernel 
The kernel exposes more minor GPU feature registers. Fill them
all into our internal feature struct.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Lucas Stach
ab942aaed0 etnaviv: don't supertile textures if supertiling is disabled via debug option 
The debug option only disables the general can_supertile spec of the GPU, so
we should also take this into account when deciding about the layout of a
sampler resource.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
 2022-04-27 09:10:27 +00:00
Samuel Pitoiset
f525706e77 radv: fix handling divisor == 0 with dynamic vertex input state 
When the divisor is 0, the compiler should generate a different VS
prolog instead of re-using a previous prolog that uses nontrivial
divisors. This is because divisor == 0 and divisor > 1 should use
a different path to guarantee that the index is correctly computed.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16009>
 2022-04-27 06:43:36 +00:00
Gert Wollny
4f3736595f r600: Add support for TGSI_OPCODE_ATOMIMIN and IMAX 
With NTT these opcodes are now emitted and need to be handled.

Fixes: a4840e15ab
   r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
 2022-04-27 00:01:20 +00:00
Gert Wollny
a8430c43a7 r600: tune nir options 
* Don't lower fp64 to software when on Cayman but
* lower fpow only when on native NIR, the TGSI backend handles
  TGSI_OPCODE_POW

Fixes: a4840e15ab
  r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
 2022-04-27 00:01:20 +00:00