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etnaviv: correct bits per tile and clear value for HALTI5

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Bits per tile and the tile clear value are not determined by the
HALTI version, but by two separate feature bits that are not always
present on HALTI5 GPUs. With big 128B/256B tile support the bits
per tile are always 4.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
This commit is contained in:
Lucas Stach
2021-01-21 15:56:18 +01:00
committed by Marge Bot
parent dd8a314d3f
commit 617339ab5b
2 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/etnaviv/etnaviv_resource.c
+3 -4
View File
@@ -85,7 +85,7 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen,
{
struct etna_screen *screen = etna_screen(pscreen);
size_t rt_ts_size, ts_layer_stride;
size_t ts_bits_per_tile, bytes_per_tile;
size_t bytes_per_tile;
uint8_t ts_mode = TS_MODE_128B; /* only used by halti5 */
int8_t ts_compress_fmt;
@@ -105,15 +105,14 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen,
if (ts_compress_fmt >= 0)
ts_mode = TS_MODE_256B;
ts_bits_per_tile = 4;
bytes_per_tile = ts_mode == TS_MODE_256B ? 256 : 128;
} else {
ts_bits_per_tile = screen->specs.bits_per_tile;
bytes_per_tile = 64;
}
ts_layer_stride = align(DIV_ROUND_UP(rsc->levels[0].layer_stride,
bytes_per_tile * 8 / ts_bits_per_tile),
bytes_per_tile *
8 / screen->specs.bits_per_tile),
0x100 * screen->specs.pixel_pipes);
rt_ts_size = ts_layer_stride * rsc->base.array_size;
if (rt_ts_size == 0)
src/gallium/drivers/etnaviv/etnaviv_screen.c
+5 -4
View File
@@ -816,11 +816,12 @@ etna_get_specs(struct etna_screen *screen)
screen->specs.can_supertile =
VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
screen->specs.bits_per_tile =
VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
!VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ||
VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE) ? 4 : 2;
screen->specs.ts_clear_value =
VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE) ? 0xffffffff :
VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 :
0x11111111;
VIV_FEATURE(screen, chipMinorFeatures10, DEC400) ? 0xffffffff :
screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555;
screen->specs.vs_need_z_div =
screen->model < 0x1000 && screen->model != 0x880;