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Author SHA1 Message Date
Kenneth Graunke e69d395cd1 intel/genxml: Add an "mbz" data type 
There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.

This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct.  We also update the decoder to handle it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
 2021-10-28 19:45:55 +00:00
Kenneth Graunke 58dc7f6ea6 intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4 
We had this field mislabeled as "Instruction Access Upper Bound", but
instruction state base address doesn't exist until Gfx5.  This is
supposed to be the upper bound for indirect object base address,
matching the G45 copy.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
 2021-10-28 19:45:55 +00:00
Pierre-Eric Pelloux-Prayer cf76247f38 drirc: enable do_dce_before_clip_cull_analysis for ANSA 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>
 2021-10-28 18:01:04 +00:00
Pierre-Eric Pelloux-Prayer 95ded68984 glsl/drirc: add an option for gl_ClipVertex / gl_CullDistance checks 
The GLSL spec says it's an error if a shader statically writes to these
2 variables.

Until this commit, Mesa refused to link a shader if it had an unused
function writing to one of these variables while another (used) function
wrote to the other.

This commit adds an option to perform dead function elimination after
the intra-stage linking step but before performing these checks.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>
 2021-10-28 18:01:04 +00:00
Dylan Baker c0fc76a172 docs: update calendar and link releases notes for 21.2.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>
 2021-10-28 17:46:35 +00:00
Dylan Baker c8bf9100cd docs: add sha256 sums for 21.2.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>
 2021-10-28 17:46:35 +00:00
Dylan Baker f07a614995 docs: add release notes for 21.2.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>
 2021-10-28 17:46:35 +00:00
Filip Gawin 021ec93273 r300: improve precission of linear interpolation 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13554>
 2021-10-28 15:23:47 +00:00
Danylo Piliaiev aa264ded94 ir3/ra: Check register file upper bound when updating preferred_reg 
Otherwise we could get invalid reg in get_reg()

Would fix many dEQP-VK.ssbo.phys.layout.*

Fixes: 0ffcb19b9d "ir3: Rewrite register allocation"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13546>
 2021-10-28 14:08:43 +00:00
shanshengwang 4f4164d62a radeon/vce: Limiting max supported refernce frames to 1 for h264 encoding 
VCE currently restricted  max_supported reference frames to 1

Signed-off-by: shanshengwang <shansheng.wang@amd.com>
Suggested-by: Suresh Guttula <suresh.guttula@amd.com>
Acked-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13543>
 2021-10-28 13:56:24 +00:00
Samuel Pitoiset d8e4546707 ac/nir: remove bogus assertion about the position for culling 
It's undefined to not export a position but some applications rely
on that. The position is always initialized to 0,0,0,1 everywhere else
if not exported.

Fixes KHR-GL46.shader_image_load_store.multiple-uniforms with Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13470>
 2021-10-28 10:44:20 +00:00
Lionel Landwerlin d3b3daa06b intel/pps: reuse timestamp_frequency from intel_device_info 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
 2021-10-28 13:16:56 +03:00
Lionel Landwerlin 43d5b55bc1 intel/pps: provide accurate min sampling period 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
 2021-10-28 13:16:56 +03:00
Lionel Landwerlin 3dda80fcf6 intel/dev: printout timestamp period 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
 2021-10-28 13:16:56 +03:00
Lionel Landwerlin 127863ddd3 docs: put a list of commands to setup perfetto 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
 2021-10-28 13:16:56 +03:00
Lionel Landwerlin bc0a702c52 pps: add an intel config file 
It was useful to set a colleague up on perfetto.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
 2021-10-28 13:16:56 +03:00
Lionel Landwerlin 32b28f2cfa pps: remove counter_ids fields 
Those appear not to be recognized anymore by perfetto.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
 2021-10-28 13:16:56 +03:00
Jordan Justen 64157c706e intel/dev/test: Assert (verx10 / 10) == ver 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13568>
 2021-10-28 09:19:07 +00:00
Rhys Perry 11602d2d36 aco: use std::vector and IDSet in RA validator 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13541>
 2021-10-28 08:55:35 +00:00
Iago Toral Quiroga b42f4b8809 broadcom/compiler: padding fixes to QPU assembly dumps 
When there are dst/src modifiers it is pretty common that instructions
take too much space and lead to alignment issues that make code a lot
harder to read, so align the MUL and SIG columns a bit wider to avoid
this:

Before:

0x380021828003faa8 fmax  rf2, rf42.abs, rf40.abs; nop
0x3800f186c503f0f0 fcmp.pushc  -, rf3, rf48; nop
0x380c038b85b83282 fmax  rf11, rf10, rf2; mov.ifa  rf14, rf46
0x3800219ab503f359 and  rf26, rf13, rf25; nop
0x3820f186c503f2f0 fcmp.pushc  -, rf11, rf48; nop           ; thrsw
0x382c013fb5b8368e and  rf63, rf26, rf14; mov.ifa  rf4, rf46; thrsw
0x38002185b503ffc4 and  rf5, rf63, rf4  ; nop
0x38002186b503f141 and  rf6, rf5, rf1   ; nop
0x382031873503f186 vfpack  tlb, rf6, rf6; nop               ; thrsw
0x380031873503f18f vfpack  tlb, rf6, rf15; nop
0x38003186bb03f000 nop                  ; nop

After:

0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs  ; nop
0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48       ; nop
0x380c038b85b83282 fmax rf11, rf10, rf2          ; mov.ifa rf14, rf46
0x3800219ab503f359 and rf26, rf13, rf25          ; nop
0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48      ; nop                         ; thrsw
0x382c013fb5b8368e and rf63, rf26, rf14          ; mov.ifa rf4, rf46           ; thrsw
0x38002185b503ffc4 and rf5, rf63, rf4            ; nop
0x38002186b503f141 and rf6, rf5, rf1             ; nop
0x382031873503f186 vfpack tlb, rf6, rf6          ; nop                         ; thrsw
0x380031873503f18f vfpack tlb, rf6, rf15         ; nop
0x38003186bb03f000 nop                           ; nop

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13545>
 2021-10-28 08:12:14 +00:00
Mike Blumenkrantz 3ad06b6949 zink: always use explicit lod for texture() when legal in non-fragment stages 
implicit lod is something else entirely

fixes #5566

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13563>
 2021-10-28 02:32:23 +00:00
Mike Blumenkrantz 4d9fc17ae8 zink: set aspectMask for renderpass2 VkAttachmentReference2 structs 
this is otherwise just garbage

fixes #5569

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13561>
 2021-10-28 02:16:15 +00:00
Mike Blumenkrantz c4a513d978 zink: use align64 for allocation sizes 
avoid 32bit sint overflows

fixes #5568

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13560>
 2021-10-28 02:01:43 +00:00
Mike Blumenkrantz 2e9e113b7f zink: cache bo SpvId array types 
this cuts down on a truckload of useless new validation spam

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13559>
 2021-10-28 01:48:17 +00:00
Yiwei Zhang 65abd1d4ae venus: implement vn_buffer_cache_entries_create 
1. advertise high hit rate cache combinations, and we should limit the
   caches to those only require device memory pool alloc
2. use size = 1 to ask for buffer memory requirements so that we do a
   sanity check on our assumption of returned size and alignment. For
   implementations don't meet our assumption, continue without cache.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang af505ff3c8 venus: implement vn_buffer_cache_get_memory_requirements 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang a74f2495ca venus: implement vn_buffer_get_max_buffer_size 
This change estimates the max_buffer_size with quick sort. Try to
avoid some traffic upon device creation time, but not worth adding a
buffer simple create api to avoid the extra requirement query traffic
since this is temporary.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang 13f2e50aee venus: add buffer cache init and usage flows 
1. struct vn_buffer_cache_entry for buffer memory requirements
2. struct vn_buffer_cache for all buffer related cached info
3. implement vn_buffer_cache_init
4. implement vn_buffer_cache_fini
5. empty vn_buffer_get_max_buffer_size
6. empty vn_buffer_cache_entries_create
7. implement vn_buffer_cache_entries_destroy
8. empty vn_buffer_cache_get_memory_requirements

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang fc237f80c6 venus: add struct vn_image_memory_requirements 
This aligns with vn_buffer_memory_requirements and can potentially
simplify future image memory requirements cache init.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang b108e096d1 venus: add struct vn_buffer_memory_requirements 
This will simplify later buffer cache api.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang 927dea7c34 venus: refactor the ahb buffer mem_type_bits query api 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang 34b7d820e2 venus: refactor to add vn_buffer_init 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang df93a8a6dd venus: refactor to add vn_device_init 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Yiwei Zhang 2a79dfb724 venus: release queues on device creation failure 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
 2021-10-28 00:23:14 +00:00
Mike Blumenkrantz 2de6beaa12 zink: add better handling for CUBE_COMPATIBLE bit 
this check was illegal because the usage bits weren't yet populated,
so add another check after usage bits are determined to figure out if
CUBE_COMPATIBLE can be applied

additionally, checking sample counts was never needed since the spec
prohibits CUBE_COMPATIBLE use with multisampling

zink DEBUG: ERR: 'Validation Error: [ VUID-vkGetPhysicalDeviceImageFormatProperties-usage-requiredbitmask ] Object 0: VK_NULL_HANDLE, type = VK_OBJECT_TYPE_DEVICE; | MessageID = 0x991b3105 | vkGetPhysicalDeviceImageFormatProperties: value of usage must not be 0. The Vulkan spec states: usage must not be 0 (https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/vkspec.html#VUID-vkGetPhysicalDeviceImageFormatProperties-usage-requiredbitmask)'

Fixes: 71494c4874 ("zink: only mark resources as cube-compatible if supported")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12580>
 2021-10-28 00:11:24 +00:00
Yiwei Zhang 5a2513a515 venus: assign valid memoryTypeIndex of exportable ahb memory for image 
The current AHB spec leaves the input memoryTypeIndex undefined when
allocating exportable AHB memory backing an external image.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13537>
 2021-10-28 00:02:54 +00:00
Bas Nieuwenhuizen 2c43fd4c41 amd/rgp: Use VGH clocks for RGP workaround. 
Hear that it matters for RGP. This is the most likely scenario where
we would hit this workaround, given the tooling for profiling on the
deck will set profile_peak as workaround for hangs.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13534>
 2021-10-27 21:51:59 +00:00
Emma Anholt bfbc41a9fa ci/piglit-runner: Merge piglit-driver-*.txt files into driver-*.txt. 
The test names are definitely unique (deqp has specific prefixes, piglit
uses '@' as a separator instead of '.'), so we can just have a single file
regardless of test type.  Merges the two groups of xfails together so you
can't mix up which file to edit (I certainly have), and so that we don't
need to introduce yet another set of files when we add gtest for libva.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13517>
 2021-10-27 20:54:11 +00:00
Emma Anholt 38dff02bfb ci/deqp-runner: Rename the deqp-drivername-*.txt files to drivername-*.txt 
We have two testsuites with the same format for fails/flakes/skips files,
and test names that are definitely unique.  As I'm about to add a third
testsuite (gtest for libva-utils), so let's have just one file each for
fails/flakes/skips instead of one per type of testsuite.  This starts the
move with just the bulk rename of deqp.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13517>
 2021-10-27 20:54:11 +00:00
Paulo Zanoni 3c49916d51 iris: destroy our mutexes a little later 
While there seems to be no bug with the state things are today, I was
recently doing some debugging and put an iris_bo_wait() before a
bo_close() in iris_bufmgr_destroy(), which caused an issue since the
bo_deps_lock mutex had already been destroyed.

Since there are quite a few things we do with the bufmgr after
destroying the mutexes, I figured we should probably postpone mutex
destruction in order to be a little safer against future code
modifications like the one I just did.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13494>
 2021-10-27 20:08:51 +00:00
Eric Engestrom e68616e5e6 docs: update calendar for 21.3.0-rc3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13557>
 2021-10-27 20:45:46 +01:00
Yiwei Zhang 9fa702f28c venus: refactor private descriptor_set helpers to be private 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13522>
 2021-10-27 18:33:11 +00:00
Sagar Ghuge 565d65baaf anv: Enable CCS for storage image formats 
v2: (Jason Ekstrand)
- Restructure if condition.
- Add early return.

v3: (Felix)
- Don't set aux_supported to false for storage image on XeHPG.

v4: (Nanley)
- Check image view format against fmt_list.
- Add helper anv_get_isl_format_with_usage.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3606>
 2021-10-27 10:59:56 -07:00
Sagar Ghuge 64ea7e5e33 anv: Pass correct aux usage while filling out surface state 
While filling out surface state, pass correct aux usage for storage
images as we support compression on XeHPG.

v2: (Jason Ekstrand)
- Move assertion down a bit
- Use general layout aux usage

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3606>
 2021-10-27 10:59:56 -07:00
Mike Blumenkrantz f79a25653b zink: move all shader bo/sharedmem access to compiler passes 
this moves more code to nir passes, which makes it easier to debug
and also allows deleting some much-more-difficult-to-read ntv code

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>
 2021-10-27 17:13:26 +00:00
Mike Blumenkrantz c18413b877 zink: add more glsl base types to get_glsl_basetype() 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>
 2021-10-27 17:13:26 +00:00
Mike Blumenkrantz 6be3c0f82d zink: move all 64-32bit shader store rewriting to nir pass 
this also enables natural 64bit stores on drivers that support it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>
 2021-10-27 17:13:26 +00:00
Mike Blumenkrantz 8a98e6fb97 zink: move shared intrinsic offset adjustments to compiler passes 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>
 2021-10-27 17:13:26 +00:00
Mike Blumenkrantz 6d31f4b7b0 zink: move ssbo store offset adjustment to compiler passes 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>
 2021-10-27 17:13:26 +00:00
Mike Blumenkrantz 150d6ee97e zink: move all 64-32bit shader load rewriting to nir pass 
this also enables natural 64bit loads on drivers that support it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>
 2021-10-27 17:13:26 +00:00