Commit Graph

7249 Commits

Author SHA1 Message Date
Timur Kristóf
e58a5cca02 nir/gather_info: Clear cross-invocation output mask.
Similar to how other I/O info is cleared at the beginning
of gather_info we should also clear the cross-invocation
mesh shader output mask.

Fixes: 112a856813
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18464>
2022-09-08 20:26:03 +00:00
Timur Kristóf
c80d811403 nir/lower_system_values: Add shortcut for 1D workgroups.
When the workgroup is 1 dimensional, simply use	a vec3
filled with zeroes and the local invocation index.
This is is better than lower_id_to_index + constant folding,
because this way we don't leave behind extra ALU instrs.

Note, this is relevant to mesh shaders on RDNA2 because
it enables us to better detect cross-invocation output
access.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18464>
2022-09-08 20:26:03 +00:00
Georg Lehmann
4d7fe94f3a nir/opt_algebraic: Optimize unpacking of upcasts to 64bit integers.
Foz-DB Navi21:
Totals from 7 (0.01% of 134913) affected shaders:
CodeSize: 213364 -> 213028 (-0.16%)
Instrs: 38347 -> 38319 (-0.07%)
Latency: 780148 -> 779776 (-0.05%)
InvThroughput: 520098 -> 519851 (-0.05%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18435>
2022-09-08 14:37:56 +00:00
Timothy Arceri
f182b1952a glsl: remove GLSL IR inverse comparison optimisations
As per 7d85dc4f35 GLSL IR is not smart enough to handle this
correctly for NANs.

Shader-db radeonsi (RX 6800):

Totals from affected shaders:
SGPRS: 26848 -> 26848 (0.00 %)
VGPRS: 13552 -> 13552 (0.00 %)
Spilled SGPRs: 134 -> 134 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 635000 -> 630988 (-0.63 %) bytes
Max Waves: 5474 -> 5474 (0.00 %)

Shader-db iris (BDW):

total instructions in shared programs: 17538859 -> 17539018 (<.01%)
instructions in affected programs: 29369 -> 29528 (0.54%)
helped: 3
HURT: 126
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.49% max: 0.49% x̄: 0.49% x̃: 0.49%
HURT stats (abs)   min: 1 max: 2 x̄: 1.29 x̃: 1
HURT stats (rel)   min: 0.27% max: 1.32% x̄: 0.61% x̃: 0.54%
95% mean confidence interval for instructions value: 1.13 1.33
95% mean confidence interval for instructions %-change: 0.54% 0.63%
Instructions are HURT.

total loops in shared programs: 4866 -> 4866 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cycles in shared programs: 858548230 -> 858548915 (<.01%)
cycles in affected programs: 1331737 -> 1332422 (0.05%)
helped: 0
HURT: 92
HURT stats (abs)   min: 2 max: 49 x̄: 7.45 x̃: 6
HURT stats (rel)   min: 0.01% max: 1.90% x̄: 0.12% x̃: 0.05%
95% mean confidence interval for cycles value: 5.72 9.17
95% mean confidence interval for cycles %-change: 0.05% 0.19%
Cycles are HURT.

Note: With the addition of "nir/comparison_pre: See through an inot to
apply the optimization", idr's shader-db results are:

All Broadwell and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19940805 -> 19940802 (<.01%)
instructions in affected programs: 582 -> 579 (-0.52%)
helped: 3 / HURT: 0

total cycles in shared programs: 858431633 -> 858431747 (<.01%)
cycles in affected programs: 4938 -> 5052 (2.31%)
helped: 0 / HURT: 3

All older Intel platforms had similar results. (Haswell shown)
total instructions in shared programs: 16715626 -> 16715670 (<.01%)
instructions in affected programs: 9496 -> 9540 (0.46%)
helped: 0 / HURT: 44

total cycles in shared programs: 881224396 -> 881232314 (<.01%)
cycles in affected programs: 600610 -> 608528 (1.32%)
helped: 6 / HURT: 44

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Ian Romanick
5473536798 nir/comparison_pre: See through an inot to apply the optimization
This also prevents some small regressions in "glsl: remove GLSL IR
inverse comparison optimisations".

shader-db results:

All Sandy Bridge and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19941025 -> 19940805 (<.01%)
instructions in affected programs: 52431 -> 52211 (-0.42%)
helped: 188 / HURT: 6

total cycles in shared programs: 858451784 -> 858431633 (<.01%)
cycles in affected programs: 2119134 -> 2098983 (-0.95%)
helped: 183 / HURT: 12

LOST:   2
GAINED: 0

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8364668 -> 8364670 (<.01%)
instructions in affected programs: 753 -> 755 (0.27%)
helped: 2 / HURT: 4

total cycles in shared programs: 248752572 -> 248752238 (<.01%)
cycles in affected programs: 87290 -> 86956 (-0.38%)
helped: 2 / HURT: 4

fossil-db results:

Skylake, Ice Lake, and Tiger Lake had similar results. (Ice Lake shown)
Instructions in all programs: 144909184 -> 144909130 (-0.0%)
Instructions helped: 6

Cycles in all programs: 9138641740 -> 9138640984 (-0.0%)
Cycles helped: 8

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Timothy Arceri
61c3438b27 nir: support loop unrolling with inot conditions
Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.

This change avoids 292 loop unrolling regressions with shader-db
once the following patch is applied.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Timothy Arceri
96c19d23c9 nir: update nir_is_supported_terminator_condition()
Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.

Here we simply check to see if the inot contains a simple
terminator condition we previously handled. We also update
the previous users of this function to use a newly name
copy of the previous behaviour
nir_is_terminator_condition_with_two_inputs().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18006>
2022-09-08 01:01:14 +00:00
Emma Anholt
7662a5e9d3 mesa: Remove PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED/lower_cs_derived.
We have fine NIR lowering for this (already called from mesa/st), no need
for a separate GLSL pass.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18361>
2022-09-06 17:11:14 +00:00
Christian Gmeiner
912d0383b4 isaspec: Move isa_decode(..) declaration
The implementation of isa_decode(..) is already part of isaspec. So lets
move the function declaration and some related structs to a src/isaspec.

Also make the header C++ safe.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18403>
2022-09-03 19:26:04 +00:00
Marcin Ślusarz
14911e8f83 spirv, compiler: add "bool nv" to shader_info.mesh
Not knowing whether we deal with the NV or EXT extension
makes implementation difficult for Intel HW.
NV support will be dropped at some point, so
this ugliness will go away eventually.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
7d1bcf1f55 spirv, nir: Handle EmitMeshTasksEXT opcode.
A task shader must use this instruction to specify the dimensions
of the launched mesh shader workgroups.
It is a terminating instruction.

When the task shader doesn't have the optional payload, use the
pre-existing launch_mesh_workgroups intrinsics.

When the task shader has a payload, use a new
launch_mesh_workgroups_with_payload_deref intrinsics which has
a deref that refers to the payload variable.

We also add this new intrinsic to nir_lower_io which lowers this
to the pre-existing explicit intrinsic.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
42e906485c spirv: Support TaskPayloadWorkgroupEXT storage class.
Just use the task_payload NIR storage class for this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
a03c30bd8d spirv: Support the CullPrimitiveEXT mesh shader built-in.
This is a per-primitive builtin output which indicates that a
primitive should be culled (deleted) from the output.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
c5c6cef893 spirv: Support EXT_mesh_shader SetMeshOutputsEXT.
Use the set_vertex_and_primitive_count intrinsic to
express the number of vertices and primitives that the
mesh shader workgroup outputs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
b3cc09cff3 spirv: Support EXT_mesh_shader mesh/task stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
bbebc1fb35 spirv: Add mesh_shading capability for EXT_mesh_shader.
Indicates support for the EXT_mesh_shader SPIR-V capabilities.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
f6925b8446 spirv: Support EXT_mesh_shader indices and mark them per-primitive.
They are not defined as per-primitive in the EXT, but they behave
like per-primitive outputs so it's easier to treat them like that.
They may still require special treatment in the backend in order to
control where and how they are stored.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Timur Kristóf
c315e2e718 vulkan, spirv: Update to Vulkan 1.3.226 and latest SPIR-V headers.
Done using the "khronos-update.py" script, leaving out parts that
are not relevant to Vulkan.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
2022-09-02 16:18:33 +00:00
Emma Anholt
e1588cdf9e spirv: Mark phis as mediump instead of directly lowering them to 16 bit.
This reverts commit 6f25d45877, replacing it
with GLSL_PRECISION_MEDIUM.  The previous commit ended up not being the
right approach, as it affected only nir vars for spirv phis and not other
nir vars, and we want a tool that does both.  The new
nir_lower_mediump_vars pass can do that for you.

No fossil-db change for my angle fossils run on radv.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>
2022-09-01 22:39:39 +00:00
Emma Anholt
0cee5f3918 nir: Add a pass to lower mediump temps and shared mem.
SPIRV and GLSL are reasonable at converting ALU ops to mediump, but
variable storage would be wrapped in a 2f32/2mp on store/load, and if
nir_vars_to_ssa doesn't make that storage go away then you'd have extra
conversions.  For compute shader shared mem, you'd waste memory too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>
2022-09-01 22:39:39 +00:00
Emma Anholt
5f66a927ec gallium,glsl: Delete PIPE_CAP_VERTEXID_NOBASE and lower_vertex_id.
Every driver uses the nir_lower_system_values path now.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18327>
2022-08-31 22:57:03 +00:00
Emma Anholt
28b2252d0a nir: Make nir_lower_discard_if() handle demotes and terminates, too.
AGX and zink both want all of these lowered, but nir_to_tgsi will want
only demote (and terminate if it was possible from GLSL but it's not)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15932>
2022-08-31 18:26:19 +00:00
Georg Lehmann
6eb4dfca23 nir/opt_algebraic: Optimize d3d9 pow with fmulz.
Foz-DB Navi21:
Totals from 69 (0.05% of 134913) affected shaders:
CodeSize: 255684 -> 253788 (-0.74%); split: -0.74%, +0.00%
Instrs: 46307 -> 46052 (-0.55%); split: -0.55%, +0.00%
Latency: 533255 -> 530742 (-0.47%); split: -0.48%, +0.01%
InvThroughput: 110001 -> 109156 (-0.77%)
VClause: 839 -> 844 (+0.60%); split: -1.19%, +1.79%
SClause: 1411 -> 1395 (-1.13%)
Copies: 1828 -> 1816 (-0.66%); split: -1.09%, +0.44%
PreSGPRs: 2243 -> 2232 (-0.49%)
PreVGPRs: 2213 -> 2192 (-0.95%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18145>
2022-08-31 17:07:24 +00:00
Georg Lehmann
9c2c47884d nir/opt_algebraic: Optimize check for single bit.
Foz-DB Navi21:
Totals from 3239 (2.40% of 134913) affected shaders:
SpillSGPRs: 110 -> 102 (-7.27%)
CodeSize: 17426512 -> 17344808 (-0.47%); split: -0.48%, +0.01%
Instrs: 3194264 -> 3179366 (-0.47%)
Latency: 20498012 -> 20481419 (-0.08%); split: -0.08%, +0.00%
InvThroughput: 3311738 -> 3311282 (-0.01%); split: -0.02%, +0.00%
SClause: 145810 -> 145690 (-0.08%)
Copies: 171748 -> 169009 (-1.59%); split: -1.63%, +0.03%
Branches: 86610 -> 86370 (-0.28%)
PreSGPRs: 138036 -> 137104 (-0.68%)
PreVGPRs: 138540 -> 138545 (+0.00%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17429>
2022-08-31 18:36:33 +02:00
Iago Toral Quiroga
a68a2805bf nir/lower_variable_initializers: implement non-scoped barrier path
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18312>
2022-08-31 07:25:00 +02:00
Emma Anholt
80b35fbefe nir/lower_mediump: Lower FS outputs to 16-bit when the value was upconverted.
Take this real-world (trimmed) shader:

precision highp float;
in lowp vec4 var_varVertexColor;
layout(location = 0) out vec4 out_FragColor0;
void main() {
    vec4 textureColor0 = vec4(1.000000e+00, 0.000000e+00, 0.000000e+00, 1.000000e+00);
    vec3 color = vec3(1.000000e+00, 1.000000e+00, 1.000000e+00);
    vec4 outColor = vec4(vec3((color).rgb), 1.000000e+00);
    (outColor *= vec4(var_varVertexColor));
    (out_FragColor0 = outColor);
}

After opts, it's just a store from input to output.  If we decide to lower
the input to 16-bit, then as long as the driver can handle 16-bit outputs,
it would be a good idea to demote the output and save the conversions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18003>
2022-08-31 02:43:45 +00:00
Jason Ekstrand
5937660067 nir: Track per-view outputs in shader_info
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17602>
2022-08-31 02:00:18 +00:00
Georg Lehmann
07b3adec12 nir: Print selection control for nir_if.
It's useful to see this information now that aco is going to use it.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18297>
2022-08-30 23:16:51 +00:00
Rhys Perry
d09b658dbd nir: use a GC context for instructions
Gives an roughly -15% change in compile-time for RADV/ACO.

Memory usage increase seems to be 5-6%.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5034
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12910>
2022-08-30 18:21:44 +00:00
Rhys Perry
69ba1c4d59 nir: adjust nir_src_copy signature to take a nir_instr *
This is almost always a nir_instr and updating the src of a nir_if will
have to work slightly differently in the future.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12910>
2022-08-30 18:21:44 +00:00
Rhys Perry
aa2d6e020b Revert "nir: Drop the unused instr arg for src/dest copy functions."
This reverts commit c3a01841184ee8303c0c5ebe58491301622c5ad6.

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12910>
2022-08-30 18:21:44 +00:00
Rhys Perry
1df320dae7 nir/serialize: remove unused parameter from read_src()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12910>
2022-08-30 18:21:44 +00:00
Connor Abbott
9d9b891f94 nir: Free instructions more often
Soon we'll be allocating instructions out of a per-shader pool, which
means that if we don't free too many instructions during the main
optimization loop, the final nir_sweep() call will create holes which
can't be filled. By freeing instructions more aggressively, we can
allocate more instructions from the freelist which will reduce the final
memory usage.

Modified from Connor Abbott's original patch to rebase on top of
refactored DCE and so that the use-after-free in nir_algebraic_impl() is
fixed.

Co-authored-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12910>
2022-08-30 18:21:44 +00:00
Daniel Schürmann
9b843f8e4a nir/opt_algebraic: a & ~a -> 0
Also re-ordered some optimizations for better readability.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18250>
2022-08-30 14:10:22 +00:00
Rhys Perry
797150c144 nir/lower_tex: ignore width of cube textures
On AMD hardware, height is faster to access and we're already doing so.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17991>
2022-08-30 07:37:08 +00:00
Rhys Perry
fc06f0cbd5 nir/print: support nir_texop_descriptor_amd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 3098000e71 ("nir: add nir_texop_descriptor_amd")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17991>
2022-08-30 07:37:08 +00:00
Marcin Ślusarz
9f3eb63878 Revert "nir/lower_task_shader: don't use base index for shared memory intrinsics"
This reverts commit e5970fe22a.

Intel backend has implemented the missing functionality.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17618>
2022-08-29 12:42:40 +00:00
Marcin Ślusarz
3531c1e315 nir/lower_task_shader: print shader after each step
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17618>
2022-08-29 12:42:40 +00:00
Qiang Yu
a19dcdf9d5 nir,ac/llvm: add nir_intrinsic_load_viewport_xy_scale_and_offset
Used by RADV/Radeonsi NGG culling. Pack them into a single vec4
load for radeonsi to reduce const buffer load.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
2022-08-26 05:50:30 +00:00
Qiang Yu
1aef9c8318 nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd
Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
2022-08-26 05:50:30 +00:00
Georg Lehmann
c8ad1aeeb2 nir/fold_16bit_tex_image: Add an option to fold image sources.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18106>
2022-08-24 17:04:03 +00:00
Gert Wollny
13355232e4 nir_lower_atomics_to_ssbo: Initialize deref struct
This fixes the use of an uninitialzed value:

Conditional jump or move depends on uninitialised value(s)
  bcmp (vg_replace_strmem.c:1203)
  _mesa_add_sized_state_reference (prog_parameter.c:434)
  st_nir_assign_uniform_locations(gl_context*, gl_program*, nir_shader*) (st_glsl_to_nir.cpp:209)
  st_finalize_nir (st_glsl_to_nir.cpp:1041)
  by 0x58271B9: st_glsl_to_nir_post_opts(st_context*, gl_program*, gl_shader_program*) (st_glsl_to_nir.cpp:571)
  ...
Uninitialised value was created by a heap allocation
  malloc (vg_replace_malloc.c:381)
  ralloc_size (ralloc.c:114)
  ralloc_array_size (ralloc.c:218)
  deref_offset_var (nir_lower_atomics_to_ssbo.c:47)
  lower_instr (nir_lower_atomics_to_ssbo.c:111)
  nir_lower_atomics_to_ssbo (nir_lower_atomics_to_ssbo.c:204)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18227>
2022-08-24 16:02:03 +00:00
Georg Lehmann
8eac45b274 nir: Add nir_ssa_scalar_is_undef.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18183>
2022-08-24 15:22:40 +00:00
Timothy Arceri
0c8492cd3b glsl: fix location for array subscript
xfb_decl_assign_location() assumes that arrays are going to be packed.
But some conditions might prevent packing (e.g: explicit location or
smooth interpolation mode).

Instead of assuming that packing will happen, this commit adds a check to
determine if it'll happen and use the result to compute the proper location.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2214

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18175>
2022-08-24 02:19:34 +00:00
Timothy Arceri
04e7ed8323 glsl: make packed varying helper needs_lowering() external
We will use this helper to correctly calculate xfb offsets in the
following patch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18175>
2022-08-24 02:19:34 +00:00
Yonggang Luo
a87195a653 glsl: Fixes [-Wdeprecated-declarations] in list_iterators.cpp
Warning messages:
../src/compiler/glsl/tests/list_iterators.cpp:68:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

../src/compiler/glsl/tests/list_iterators.cpp:187:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
2022-08-23 15:19:16 +00:00
Yonggang Luo
fd516fca15 nir: Fixes [-Wdeprecated-declarations] in serialize_tests.cpp
Warning messages:
../src/compiler/nir/tests/serialize_tests.cpp:113:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

../src/compiler/nir/tests/serialize_tests.cpp:119:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
2022-08-23 15:19:16 +00:00
Erik Faye-Lund
b08f293686 glsl/tests: do not perform eol-conversion on windows
These tests fail on Windows, because we open the expected files in
text-mode, performing EOL conversion. Instead, let's read them as binary
files, and manually UTF-8 decode them to get the expected result.

This fixes the tests on Windows for me.

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18179>
2022-08-23 09:16:19 +00:00
Ian Romanick
2b3e1d587d glsl: Remove lower_offset_arrays pass
It is no longer used.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547>
2022-08-23 01:10:23 +00:00
Ian Romanick
dbd022f2ab nir: spirv: Allow 32-bit version of nir_intrinsic_is_sparse_texels_resident
This intrinsic returns a Boolean.  Both 1-bit and 32-bit versions must
be allowed.  Otherwise, size mismatches will occur after lowering
1-bit Booleans to 32-bit.

Fixes: 4cbdf9ec4d ("nir,spirv: implement SpvOpImageSparseTexelsResident")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547>
2022-08-23 01:10:23 +00:00