Marcin Ślusarz 9f3eb63878 Revert "nir/lower_task_shader: don't use base index for shared memory intrinsics" ...

This reverts commit e5970fe22a.

Intel backend has implemented the missing functionality.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17618>

2022-08-29 12:42:40 +00:00

..

clc

nir: add a nir_opt_if_options enum

2022-08-10 12:55:39 +00:00

glsl

glsl: fix location for array subscript

2022-08-24 02:19:34 +00:00

isaspec

isaspec: Handle patterns bigger then 64 bit

2022-06-14 12:35:39 +00:00

nir

Revert "nir/lower_task_shader: don't use base index for shared memory intrinsics"

2022-08-29 12:42:40 +00:00

spirv

nir: spirv: Allow 32-bit version of nir_intrinsic_is_sparse_texels_resident

2022-08-23 01:10:23 +00:00

builtin_type_macros.h

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glsl_types.cpp

compiler/types: Don't place members in the previous substruct's end padding

2022-06-09 22:55:37 +00:00

glsl_types.h

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meson.build

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nir_gl_types.h

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nir_types.cpp

nir/types: fix glsl_matrix_type_is_row_major() assert

2022-06-30 00:41:46 +00:00

nir_types.h

nir/glsl: wrap component_slots_aligned()

2022-05-16 03:33:18 +00:00

shader_enums.c

nir+ir3: Rename load_size_ir3 to load_center_rhw_ir3.

2022-07-11 16:56:05 +00:00

shader_enums.h

gallium: use gl shader types as the basis for the gallium ones

2022-08-04 08:17:39 +00:00

shader_info.h

nir: add uses_bindless flag for shader_info

2022-08-17 21:53:02 +00:00