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Author SHA1 Message Date
Mike Blumenkrantz
d364faa322 zink: set VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT on zs rts 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
 2021-06-09 17:26:52 +00:00
Mike Blumenkrantz
652db34f8a zink: populate maxSampleLocationGridSize for all available sample sizes on init 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11189>
 2021-06-09 17:26:52 +00:00
Timur Kristóf
1e49018ced amd: Add extra source to the mbcnt_amd NIR intrinsic. 
The v_mbcnt instructions can take an extra source that they add to
the result. This is not exposed in SPIR-V but we now expose it in NIR.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
f6b2db298f ac/nir: Refactor and optimize the repacking sequence. 
According to feedback, the terminology with "exclusive scan"
and "reduction" is difficult. Change it to use "repack" instead,
which better fits what this sequence is actually used for.

The new sequence stores only 1 byte / wave to LDS, and uses packed
instructions to produce the results. This has lower latency and
fewer instructions than what we previously had.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
b4e22eb482 aco: Keep VGPR destinations for uniform shared loads when beneficial. 
When the result of these loads is only used by cross-lane instructions,
it is beneficial to use a VGPR destination. This is because this allows
to put the s_waitcnt further down, which decreases latency.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
ce141e4c5f aco: Implement byte and lane permute intrinsics. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
43ce80a58f nir: Add AMD-specific byte and lane permute intrinsics. 
These map directly to v_perm_b32 and v_permlane_b32.
Unfortunately there is no corresponding NIR opcode or
intrinsics, and it's too tedious to puzzle these things
together from the existing NIR instructions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
5713e059ea aco: Add validation for v_permlane instructions. 
Previously there hasn't been any validation for these instructions,
but after shooting myself in the leg with it a few times, I decided
to add the validation now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
fd6605367d aco: Implement nir_op_sad_u8x4. 
Fix up the operand size for v_sad instructions, and implement
the new NIR horizontal add. There is no viable way to do this
in SALU, so let's always use a VGPR destination.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
c92dab8e2b nir: Add nir_op_sad_u8x4 which corresponds to AMD's v_sad_u8. 
NIR currently doesn't have any intrinsics for a horizontal packed add,
so this one is modeled after AMD's v_sad_u8.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Timur Kristóf
228169c87c aco: Add note about v_alignbyte in the ISA README. 
We tried to use this instruction for a more optimal sequence,
but it turned out that it doesn't exactly work as it was
supposed to. This note is to help others who want to use it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
 2021-06-09 16:48:51 +00:00
Michel Zou
fe625241f7 llvmpipe: restrict optim bug workaround to gcc 10.x 
seems fixed in 11.x, see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3906

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11209>
 2021-06-09 16:19:16 +00:00
Ilia Mirkin
cabafa5ed8 mesa: always expose NV_image_formats and OES_shader_image_atomic 
As a result of some previous changes, it is now possible to expose ES
3.1 without having the ARB_shader_image_load_store enable set. However
we still want those other extensions. When there's a driver that's
capable of exposing ES 3.1 but not these extensions, more caps can be
added.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11204>
 2021-06-09 15:50:55 +00:00
Hoe Hao Cheng
e51097b938 zink: remove variable length arrays in ntv 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11171>
 2021-06-09 15:08:38 +00:00
Mike Blumenkrantz
fa8eca1605 util/prim_restart: simplify util_draw_vbo_without_prim_restart a bit 
by initilizing variables up front and using actual draw structs for the
rewrite, a multidraw can be passed to the driver

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
 2021-06-09 14:17:38 +00:00
Mike Blumenkrantz
aa78326e12 util/prim_restart: update index bounds before draws in util_draw_vbo_without_prim_restart 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
 2021-06-09 14:17:38 +00:00
Mike Blumenkrantz
1627476079 util/prim_restart: store the total index count when rewriting draws 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
 2021-06-09 14:17:38 +00:00
Mike Blumenkrantz
aee78a3504 util/prim_restart: store index bounds while rewriting draws 
may as well

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
 2021-06-09 14:17:38 +00:00
Mike Blumenkrantz
69d47fdd7a util/prim_restart: pre-trim degenerate primitives during draw rewrite 
these will be eliminated by drivers anyway

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
 2021-06-09 14:17:38 +00:00
Mike Blumenkrantz
5d54b64e6d util/prim_restart: assert the index size at the start of the function 
this lets it be removed from the macro loop

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10966>
 2021-06-09 14:17:38 +00:00
Rhys Perry
c129ede523 aco: use ds_read_{u8,u16}_d16 
This allows partial writes and writes to the upper half of the destination.

fossil-db (Sienna Cichlid):
Totals from 135 (0.09% of 149839) affected shaders:

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
 2021-06-09 12:06:50 +00:00
Rhys Perry
6334d73fc9 aco: don't ever widen 8/16-bit sgpr load_shared 
Doesn't seem to create incorrect code, but it is suboptimal.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
 2021-06-09 12:06:50 +00:00
Rhys Perry
d2b9c7e982 radv: improve LDS alignment check for load/store vectorization 
Previously, this could vectorize two scalar 16-bit loads into a u8vec4
load.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
 2021-06-09 12:06:50 +00:00
Rhys Perry
4870d7d829 aco: use v1b/v2b for ds_read_u8/ds_read_u16 
The p_extract_vector isn't necessary.

For ds_read_u8 and ds_read_u16, we used a 32-bit regclass, but did't load
32 bits, and used dst_hint for vector loads when we shouldn't have.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4863
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11113>
 2021-06-09 12:06:50 +00:00
Samuel Pitoiset
2fb436e92a ci: update list of expected failures for Pitcairn/Oland (RADV) 
The robustness2 failures were a mistake because they are actually
not supported (no VK_EXT_scalar_block_layout on GFX6).

The sparse related failures are no longer supported since sparse
is only enabled for Polaris10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11243>
 2021-06-09 11:27:44 +00:00
Samuel Pitoiset
d169dad393 aco: fix emitting literal offsets with SMEM on GFX7 
When the offset is negative, reg() isn't 255. Fix this by splitting
SGPR and literal emission. While we are at it, adjust a comment
saying that literals are also accepted on GFX6 which is wrong.

Fixes another batch of robustness tests.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11247>
 2021-06-09 11:10:38 +00:00
Daniel Stone
6c6674d72c ci/zink: Skip flaky GLX test 
!11218 definitely didn't change anything about Zink that should make it
read black back from GLX. Assuming it's a race somewhere, just add it to
skips and move on.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11256>
 2021-06-09 10:24:56 +00:00
Samuel Pitoiset
13efad3086 radv: dump SPIR-V instead of using spirv-dis when generating a hang report 
Useful when spirv-dis isn't found.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11034>
 2021-06-09 10:07:17 +00:00
Georg Lehmann
3149eccc1c radv: Implement VK_EXT_global_priority_query. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11215>
 2021-06-09 08:25:25 +00:00
Georg Lehmann
00084669ae vulkan: Update the XML and headers to 1.2.180 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11215>
 2021-06-09 08:25:25 +00:00
Paulo Zanoni
697804ba49 iris: finish converting from drmIoctl to intel_ioctl 
Only 3 remaining users. The implementations are exactly the same.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11194>
 2021-06-09 08:00:55 +00:00
Caio Marcelo de Oliveira Filho
e94c99513a nir/gather_info: Rename per_vertex to is_arrayed 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
 2021-06-09 07:35:57 +00:00
Caio Marcelo de Oliveira Filho
a59f1d628a nir/lower_io: Rename vertex_index to array_index in helpers 
The helpers will be reused for per-primitive variables that are also
arrayed, so use a more general name.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11252>
 2021-06-09 07:35:57 +00:00
Samuel Pitoiset
3761d994f6 aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7 
GFX6-7 are affected by a hw bug that prevents address clamping to work
correctly when the SGPR offset is used. Use the VGPR offset to fix it.

Fixes various hangs with dEQP-VK.robustness.robustness2.* on Bonaire.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11238>
 2021-06-09 06:40:16 +00:00
Tomeu Vizoso
d523126bd0 ci: Disable windows builds due to runner not being available 
Warning from Gitlab:

This job is stuck because you don't have any active runners online or
available with any of these tags assigned to them: windows shell 1809
mesa

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
 2021-06-09 07:37:45 +02:00
Alyssa Rosenzweig
95bd6e915f nir/lower_fragcolor: Avoid redundant load_output 
At best, this is an extra instruction for NIR to optimize out. At worst,
depending on pass ordering nir_load_output could sneak into the final
NIR, even on drivers that don't support fbfetch.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
 2021-06-09 02:58:08 +00:00
Alyssa Rosenzweig
209c829775 ci: Disable the iris APL jobs 
Someone's cat is chewing on the Ethernet adaptor.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11255>
 2021-06-09 02:58:08 +00:00
Rob Clark
09f64f74db freedreno/ir3: Fix use after free 
If the tex/sfu ssa src is from a different block than the one currently
being scheduled, we do not have a valid sched-node.  So fallback to
previous behavior rather than dereference an invalid ptr.

Fixes: 7821e5a3f8 ("ir3/sched: Don't penalize uses of already-waited tex/SFU")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10306>
 2021-06-09 00:37:15 +00:00
Jason Ekstrand
ddf970af88 anv/blorp: Optimize addresses/relocations when ANV_ALWAYS_SOFTPIN 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
c7e1488037 anv: Optimize anv_address_physical when ANV_ALWAYS_SOFTPIN 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
921bd2d1c7 anv: Fast-path surface relocs when we have softpin 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
6afc3f97b6 anv: Make anv_batch_emit_reloc inline and optimize SKL+ 
This should drop the CPU overhead of processing buffers on SKL+ by
dropping some of the logic contained in anv_reloc_list_add() whenever we
have enough compile-time information to know we have softpin.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
9802a0d7ca anv: Add a helper to add a BO to the batch list without a reloc 
The relocation list currently serves two purposes.  One is for
relocations on older non-softpin platforms.  The second is to keep track
of driver-managed BOs which are used by the given command buffer.  We
going to need a mechanism to add BOs to the command buffer without doing
a relocation into the batch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
7e8c28383c anv: Handle OOM in the pinned path in anv_reloc_list_add 
Fixes: b3c0b1b218 "anv: Use a bitset for tracking residency"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
a63e97e09a anv: Make use_softpin compile-time in genX code 
Whenever we have the GFX_VERx10 macro available, we can make use_softpin
a compile-time thing for everything but Broadwell and Cherryview.  This
should save us some CPU cycles especially on SKL+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Jason Ekstrand
04ccfeae98 anv: Require softpin on Gen8+ 
Softpin was added to i915 in

    commit 506a8e87d8d2746b9e9d2433503fe237c54e4750
    Author: Chris Wilson <chris@chris-wilson.co.uk>
    Date:   Tue Dec 8 11:55:07 2015 +0000

        drm/i915: Add soft-pinning API for execbuffer

which was included in Linux 4.5.  It's been over 5 years so it's
probably reasonable to make it a hard requirement.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
 2021-06-08 22:53:22 +00:00
Caio Marcelo de Oliveira Filho
7c1c9e935e anv: Support workgroup memory in other shaders 
Mesh and Task shaders can use workgroup memory, so generalize its
handling in anv by moving it from anv_pipeline_compile_cs() to
anv_pipeline_lower_nir().

Update Pipeline Statistics accordingly.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11230>
 2021-06-08 11:30:39 -07:00
Caio Marcelo de Oliveira Filho
8af6766062 nir: Move workgroup_size and workgroup_variable_size into common shader_info 
Move it out the "cs" sub-struct, since these will be used for other
shader stages in the future.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
 2021-06-08 09:23:55 -07:00
Caio Marcelo de Oliveira Filho
b5f6fc442c nir: Move zero_initialize_shared_memory into common shader_info 
Move it out the "cs" sub-struct, since the bit will be used for other
shader stages in the future.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11225>
 2021-06-08 09:23:55 -07:00
Mike Blumenkrantz
7b13c1461d zink: more accurately handle shader layer/viewport caps 
the spirv extension is required for spirv < 1.5, but the core cap should
be used for spirv >= 1.5

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11244>
 2021-06-08 15:40:22 +00:00