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Author SHA1 Message Date
Alyssa Rosenzweig
16e6657132 pan/indirect_draw: Fix 1 instance, nonzero divisor 
Instead of doing a complicated hack with the POT divisor, just zero the
stride of the linear attribute buffer like we do on the CPU.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
14da452598 pan/indirect_draw: Use unsigned comparisons 
Instead of signed -- get the types right.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
5ea73dbed9 pan/indirect: Factor out is_power_of_two_or_zero 
The function is complicated enough as it is -- hide the bit twiddling
behind a helper function.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
c25a40d535 panfrost: Default indirect attributes to 1D type 
Avoids some complexity in the indirect draw happy path.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
0566fa2db4 panfrost: Use util_last_bit for images 
Probbaly more correct for hols in image_mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
619b1bc23b panfrost: Be explicit in image modifier handling 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
5ed37ebfee panfrost: Separate image attribute and buffer emit 
Trying to disentangle attributes and attribute buffers, so here's
a leaf node for that change.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
f14dbc02fb panfrost: Don't duplicate attribute buffers 
If the (vbi, divisor) tuple matches, we can save an attribute buffer
descriptor. We do the linking at CSO create time. This should be a bit
more cache friendly.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
61b83fba27 panfrost: Disable AFBC on v7 
Broken in several ways. Hide it until we can get this sorted, and have a
test plan to keep it sorted.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
655983d328 panfrost: Add missing 'Reverse issue order flag' 
Should fix an issue I'm seeing. Spoiler alert, it does not.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
317dd5b327 panfrost: Remove AFBC format fixups 
It's too complicated and probably for no actual benefit. The main reason
we have BGR formats is for display, but that's export and doesn't get
hit by this path. Internal BGRA textures are possible with a Mesa
extension but sufficiently rare that I regret suggesting this as a
possible optimization. My apologies, and thanks for the fish.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
e111464bfc pan/bi: Don't allocate past the end of the reg file 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
47e0cce820 pan/bi: Track words instead of bytes in RA 
Reduces RA memory footprint by 4x, fixing an OOM in the following dEQP
test that otherwise would allocate 8GB of memory...

   dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
dbc346d659 pan/bi: Simplify spill code 
Now allow spilling all nodes. Fixes failed spilling in

dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.21

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
6dbaae77d9 pan/bi: Emit a dummy ATEST if needed 
Match what the blob does, since Bifrost has so many random errata we'd
be fools not to.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
b947ab8b10 pan/bi: Lower 64-bit ints again 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
95458c4033 pan/bi: Lower stores with component != 0 
If the shader packs multiple varyings into the same location with
different location_frac, we'll need to lower to a single varying store
that collects all of the channels together. This is not trivial during
code gen, but it is trivial to do in NIR right before codegen by relying
on nir_lower_io_to_temporaries. Since we're guaranteed all varyings will
be written exactly once, in the exit block, we can scan the shader
linearly and collect stores together in a single pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
de42707101 pan/bi: Lower loads with component > 0 
We have no native way to swizzle out a nonzero component in a load, but
we can simply load extra components and do the swizzle in shader
instructions. This is inefficient, since it loads data to discard
immediately, but it's required for conformance in some edge cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
5c0e5d4d2d pan/bi: Handle images in vertex shaders 
We need to offset by the number of attributes, since the primary
attribute table is shared for images and vertex attributes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
071165e082 pan/bi: Model +BLEND clobbering of r48 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
4663afd8ab pan/bi: Don't restrict the register file in non-blend shaders 
Now that preloading is handled correctly, there's nothing 'special'
about R59 and up, so this gets us a few more registers to work with.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
35c7fefc8f pan/bi: Allow move/sink in blend shaders 
Now that we handle precolouring we don't need to workaround anything.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
3d851f3b8e pan/bi: Model interference with preloaded regs 
Now that we have affinity masks in RA, we can handle this as an easy
case of register liveness analysis, rather than creating pseudo-nodes
and trying hard to coalesce the resulting moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
8d4ce240be pan/bi: Explicit zero reg_live_{in, out} when needed 
I want to use these fields for a similar purpose in the register
allocator, so they won't be zero anymore for scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
98f072e21b pan/bi: Inline spilling in RA 
Should be faster for both spill and not spill cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
80a58dc2e6 pan/bi: Use explicit affinities in RA 
Inline LCRA to allow us to make the change without disrupting Midgard,
and get some nice cleanup from doing so.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
9d7e25a9a9 pan/bi: Allow IADD.u32 on FMA as *IADDC 
There's a common special case, slight boost in scheduler freedom.

total nops in shared programs: 101130 -> 101048 (-0.08%)
nops in affected programs: 1677 -> 1595 (-4.89%)
helped: 13
HURT: 0
helped stats (abs) min: 6 max: 8 x̄: 6.31 x̃: 6
helped stats (rel) min: 3.24% max: 25.00% x̄: 7.42% x̃: 4.48%
95% mean confidence interval for nops value: -6.76 -5.85
95% mean confidence interval for nops %-change: -12.02% -2.81%
Nops are helped.

total clauses in shared programs: 27076 -> 27075 (<.01%)
clauses in affected programs: 8 -> 7 (-12.50%)
helped: 1
HURT: 0

total quadwords in shared programs: 113142 -> 113113 (-0.03%)
quadwords in affected programs: 1935 -> 1906 (-1.50%)
helped: 13
HURT: 0
helped stats (abs) min: 2 max: 4 x̄: 2.23 x̃: 2
helped stats (rel) min: 0.95% max: 7.50% x̄: 2.16% x̃: 1.26%
95% mean confidence interval for quadwords value: -2.59 -1.87
95% mean confidence interval for quadwords %-change: -3.45% -0.88%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
7aefd6c1ba pan/bi: Track liveness while scheduling 
If we know that a value is killed in the next tuple, there is no need to
write it out to the register file. We already handled this as a packing
fixup. However, avoiding this write also frees up an extra slot in the
register block, which offers additional scheduling freedom. To take
advantage of this, we extend liveness analysis to work while scheduling,
and modify the schedulable predicate accordingly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
20809daa9a pan/bi: Add post-RA optimizer 
Delete coalesced moves. Now this is trivial! See e.g shaders/tesseract/118.shader_test

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
4ed000cf3f pan/bi: Bundle after RA 
Flag day change to swap the order of the "scheduler" with the register
allocator. This gives RA much more freedom without significantly
hndering bundling.

It also opens up the door to Adult-level Scheduling which would occur
prior to bundling.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
afa4a1d496 pan/bi: Fix bi_rewrite_passthrough ordering 
The ordering is irrelevant for SSA form input, but is very relevant for
register input.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:10 +00:00
Alyssa Rosenzweig
246beb15cf pan/bi: Simplify TEXC codegen for sr_count=0 
Obscure case.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:09 +00:00
Alyssa Rosenzweig
de8fe8c0b1 pan/bi: Use TEXS_2D for rect textures 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:09 +00:00
Alyssa Rosenzweig
6f51bd99f2 pan/bi: Pull out bi_count_write_registers 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
 2021-06-10 18:06:09 +00:00
Yiwei Zhang
02832f9d03 vulkan: fix back compat with Android Oreo and below 
buffer_handle_t definition was previously inside the deprecated
system/core/include/system/window.h.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11301>
 2021-06-10 17:41:34 +00:00
Neha Bhende
8a3fa2c4d5 svga: Initialize pipe_shader_state for transform shaders 
This fixes crashes for opengl apps. Issue is found in vmware
internal testing

Fixes: f01c0565bb ("draw: free the NIR IR.")

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11274>
 2021-06-10 17:28:41 +00:00
Mike Blumenkrantz
e39b6951cc util/blitter: remove duplicated set_sample_mask calls 
it doesn't make sense to have both, so just keep the simpler one

no functional changes because this was redundant

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11294>
 2021-06-10 16:58:14 +00:00
Adam Jackson
f535ab59e2 swrast: Fix a warning from gcc 11 
gcc 11 dixit:

   In function ‘sample_2d_ewa’,
       inlined from ‘sample_lambda_2d_aniso’ at ../src/mesa/swrast/s_texfilter.c:1995:10:
   ../src/mesa/swrast/s_texfilter.c:1729:13: warning: ‘sample_2d_nearest’ reading 16 bytes from a region of size 8 [-Wstringop-overread]
    1729 |             sample_2d_nearest(ctx, samp, img, newCoord, rgba);
         |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   ../src/mesa/swrast/s_texfilter.c: In function ‘sample_lambda_2d_aniso’:
   ../src/mesa/swrast/s_texfilter.c:1729:13: note: referencing argument 4 of type ‘const GLfloat *’ {aka ‘const float *’}

Indeed, newCoord is GLfloat[2] but the argument is typed GLfloat[4],
even though only the first two (s and t) are ever read. Fix the array
size in the function signature to reflect the maximum element actually
addressed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11273>
 2021-06-10 16:20:09 +00:00
Roman Stratiienko
5987f71cb1 nouveau: Don't require RTTI and use it only when enabled 
The only case RTTI is used in nouveau is type assertion at:
File src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:

    assert(typeid(*i) == typeid(*this));

This assertion is used 'to be on the safe side' only and not mandatory.

In Android we do not have rtti for libLLVM therefore this assertion
has to be skipped.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11069>
 2021-06-10 15:10:04 +00:00
Charlie
f389676173 v3dv: enable KHR_uniform_buffer_standard_layout 
We already support this memory layout. All relevant CTS tests seem to
pass

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
 2021-06-10 15:04:23 +01:00
Charlie
c8dffda633 v3dv: enable KHR_incremental_present 
All bits should already be provided by wsi/common.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
 2021-06-10 15:04:12 +01:00
Charlie
1c97d06a68 v3dv: enable KHR_sampler_mirror_clamp_to_edge 
This is already implemented

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
 2021-06-10 15:03:04 +01:00
Charlie
be2b11003a v3dv: enable KHR_image_format_list 
There's nothing checking for mutable formats, so this needs no changes

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
 2021-06-10 15:03:03 +01:00
Rhys Perry
7c63ec70ef nir: document that ACCESS_RESTRICT is not set at intrinsics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
 2021-06-10 13:17:22 +00:00
Rhys Perry
938098c98d nir/opt_load_store_vectorize: only require one variable to be restrict 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
 2021-06-10 13:17:22 +00:00
Rhys Perry
865ca3af2b nir/opt_load_store_vectorize: check for restrict at the variable 
SPIR-V -> NIR doesn't set ACCESS_RESTRICT at the intrinsic.

fossil-db (GFX10.3):
Totals from 3 (0.00% of 139391) affected shaders:
CodeSize: 12364 -> 12356 (-0.06%)
Instrs: 2493 -> 2494 (+0.04%); split: -0.04%, +0.08%
Cycles: 15279372 -> 15295756 (+0.11%); split: -0.11%, +0.21%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
 2021-06-10 13:17:22 +00:00
Rhys Perry
2e7bceb220 nir/load_store_vectorizer: fix check_for_robustness() with indirect loads 
fossil-db (GFX10.3, robustness2 enabled):
Totals from 13958 (9.54% of 146267) affected shaders:
VGPRs: 609168 -> 624304 (+2.48%); split: -0.05%, +2.53%
CodeSize: 48229504 -> 48488392 (+0.54%); split: -0.02%, +0.56%
MaxWaves: 354426 -> 349448 (-1.40%); split: +0.00%, -1.41%
Instrs: 9332093 -> 9375053 (+0.46%); split: -0.03%, +0.49%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
 2021-06-10 13:17:22 +00:00
Charlie Birks
674b0af3b3 v3dv: document two supported extensions 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11268>
 2021-06-10 13:13:03 +00:00
Rhys Perry
6204e17b44 radv: increase maxComputeSharedMemorySize 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11262>
 2021-06-10 12:55:53 +00:00
Rhys Perry
9162963f0a aco: fix emit_mbcnt() with a VGPR mask 
Found by inspection. Should be possible with nir_intrinsic_mbcnt_amd.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11295>
 2021-06-10 11:21:47 +00:00