Commit Graph

166536 Commits

Author SHA1 Message Date
Jesse Natalie d7f9e2db59 dzn: Get options4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 08fc7315c5 dzn: Delete unused extensions table
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie cc906c0eed dzn: Enable get_surface_capabilities2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie a7d4309234 spirv2dxil: Support 16bit types
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 536ab16bc1 spirv2dxil: Move shader model into runtime conf struct
We'll want to use it to control the shape of the nir that we generate

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 4c527f4fc0 spirv2dxil: Lower unaligned loads and stores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 9e2683c6f0 spirv2dxil: Set min UBO/SSBO alignments
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 58e7acb0e2 microsoft/compiler: Support lowering SSBO accesses to 16bit vectors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 0f56fc09d9 microsoft/compiler: Support raw buffer load/store intrinsics with 16bit alignment
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 196dc72838 microsoft/compiler: Handle 48-bit stores to SSBO/shared
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie c994c8b3fd microsoft/compiler: Pass an alignment to constant buffer load lowering
This means we can stop doing conditionals and shifts if we know the
alignment of a load for a small amount of data.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 7fcb60be37 microsoft/compiler: Simplify bitpacking for load/store lowering with nir_extract_bits
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 7830901751 microsoft/compiler: Pass deref modes to unaligned pass and handle push const
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie facd2e4fdb microsoft/compiler: Move unaligned load/store pass from CL
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie f50843fcdb microsoft/compiler: Handle undef-rounding f2f16 as rtz
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 8782a0b8df microsoft/compiler: Ensure native_low_precision is set for 16-bit bitcasts/stores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 4d76d46c13 microsoft/compiler: Handle frcp for float16/float64
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie ed13c2261c microsoft/compiler: Handle struct consts in DXIL module dumper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 25ee07373c nir_lower_fp16_casts: Allow opting out of lowering certain rounding modes
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie c0c2b60f1d nir: Add alignment to load_push_constant
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21029>
2023-02-11 06:12:23 +00:00
Jesse Natalie 42267588d7 ci/windows: Update LLVM to 15
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21168>
2023-02-11 05:24:08 +00:00
Jesse Natalie e9ab33c9a1 microsoft/clc: Set features that are used by CL tests
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21168>
2023-02-11 05:24:08 +00:00
Jesse Natalie b27d8ee2e9 clc: Include opencl-c-base.h with LLVM 15 (using builtins)
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21168>
2023-02-11 05:24:08 +00:00
Jonathan Marek dda35e616b turnip: fix use of align() instead of util_align_npot() with tile_align_w
tile_align_w isn't always a power of two.

Fixes: aae679e221

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21251>
2023-02-11 04:56:52 +00:00
Karol Herbst cb611b207d rusticl/icd: Make it work in case Rustc shuffles struct around
Nothing guarentees fields are in order or anything like that. So do proper offset math

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21242>
2023-02-11 04:13:57 +00:00
Karol Herbst f6c5cd33b0 rusticl/util: extract offset_of macro
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21242>
2023-02-11 04:13:57 +00:00
Faith Ekstrand af9212dd82 nir/deref: Preserve alignments in opt_remove_cast_cast()
This also removes the loop so opt_remove_cast_cast() will only optimize
cast(cast(x)) and not cast(cast(cast(x))).  However, since nir_opt_deref
walks instructions top-down, there will almost never be a tripple cast
because the parent cast will have opt_remove_cast_cast() run on it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21252>
2023-02-10 23:08:19 +00:00
Sviatoslav Peleshko 9b2ddd2c5e anv: Handle VkAccelerationStructureBuildRangeInfoKHR::transformOffset
Previously it was not actually handled. This meant that all geometries
with the same transform buffer were using the same (first) transformation
matrix.

Fixes: f3ddfd81 ("anv: Build BVHs on the GPU with GRL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7575
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21227>
2023-02-10 21:27:14 +00:00
Marcin Ślusarz 465c241266 intel/compiler/mesh: use U888X packed index format
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20910>
2023-02-10 21:03:33 +00:00
Danylo Piliaiev 2d20564a6a turnip: Disable draw states after dyn renderpass in all cases
Draw states were not disabled after a dynamic renderpass which
spans several command buffers, the next renderpass if started in
the same command buffer wouldn't emit the full draw state,
since TU_CMD_DIRTY_DRAW_STATE was not set by previous renderpass.

The issue could be observed when corrupting all regs at cmdbuf start in:
 dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed7_geometry

Fixes: cb0f414b2a
("tu: Add support for suspending and resuming renderpasses")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Danylo Piliaiev 855fa78866 turnip: Ensure that there is no renderpass rotation in binning
It appears that A6XX_GRAS_SC_CNTL::rotation applies to the binning,
so we should ensure there is no unexpected rotations and apply with
A6XX_GRAS_SC_CNTL during the binning pass.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Danylo Piliaiev 43ea1f2dfb freedreno: Document A6XX_GRAS_SC_CNTL::rotation field
Likely used for VK_QCOM_render_pass_transform.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Danylo Piliaiev 388e4ea733 tu: Prevent using stale value of GRAS_SC_CNTL in sysmem clear
cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Danylo Piliaiev 981f1d88a1 tu: Prevent using stale value of RB_UNKNOWN_88D0 on BLIT
Fixes: def56b531c
("tu: Support GMEM with layered rendering and multiview")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Amber 99fb770c45 freedreno: use blendcoherent to set FLUSH_PER_OVERLAP
FLUSH_PER_OVERLAP is only necessary for gmem if coherent blending is
enabled.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
2023-02-10 20:01:43 +00:00
Amber 527a74cb5d gallium: make BlendCoherent usable from gallium drivers
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
2023-02-10 20:01:43 +00:00
Amber 40bdd2bbf7 freedreno: use A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE with fb readback
fixes:
dEQP-GLES31.functional.blend_equation_advanced.msaa.*

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
2023-02-10 20:01:43 +00:00
Mike Blumenkrantz cd446b87e1 zink: add newlines to some debug printfs
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21239>
2023-02-10 19:42:53 +00:00
Väinö Mäkelä 13f68bcce1 hasvk: Tell spirv_to_nir float controls are always supported
This gets rid of the "Unsupported SPIR-V capability" warnings when
compiling shaders using float controls on gfx7.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:01 +00:00
Väinö Mäkelä 6f932276c3 hasvk: Don't claim shaderDenormPreserveFloat32 on gfx7
From the Haswell PRM Vol. 7, "IEEE Floating Point Mode":
     "Single precision (F, Float) denorms are flushed to sign-preserved
      zero on input and output of any floating-point mathematical
      operation."

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:01 +00:00
Väinö Mäkelä 56667002fd intel/vec4: Don't optimize multiply by 1.0 away
The SPIR-V compiler's implementation of tanh generates a multiply by 1.0
to flush denorms to zero.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:01 +00:00
Väinö Mäkelä dcad4a2cd1 intel/vec4: Set the rounding mode
The rounding mode only needs to be set once, because 16-bit floats or
preserving denorms aren't supported for the platforms where vec4 is
used.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:00 +00:00
Eric Engestrom 5a2326f9b2 panfrost: drop no-longer-needed libglsl
Fixes: 551c2aadd4 ("pan/bi: Remove standalone compiler")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21240>
2023-02-10 14:09:37 +00:00
Samuel Pitoiset bd30f3619d radv: implement graphics shaders relocation for a RGP workaround
RGP requires shaders to be uploaded consecutively inside the same
buffer object. Otherwise, either it makes the driver generating
huge traces (ie. in GiB) or it fails to load traces at all. Hopefully,
this will be improved soon when AMDGPU drivers will have GPL support.

To workaround this, the driver relocates graphics shaders in the same
buffer object when a pipeline is created. Then at draw time, it
overwrites SPI_SHADER_PGM_xxx registers to make sure SQTT can match
between emitted and exported shaders. It's a bit suboptimal because
graphics shaders are uploaded twice but it's the best solution I found.

This will allow to implement GPL caching without breaking capturing
shaders with RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21078>
2023-02-10 13:42:14 +00:00
Samuel Pitoiset 69bd1c0c40 radv: restore uploading shaders individually instead of consecutively
The shaders were uploaded consecutively to fit a RGP constraint but
this was more like a workaround. This upload path doesn't work well for
graphics pipeline library and it was the main blocker for GPL caching.

This commit breaks capturing shaders with RGP if the offset between
shaders is too big. Next commit should fix it by using shaders reloc.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21078>
2023-02-10 13:42:14 +00:00
Georg Lehmann 533d0008c7 aco: remove stale TODOs about v_interp opsel
These are already handled correctly according to the ISA docs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21096>
2023-02-10 12:01:56 +00:00
Philipp Zabel f29f656530 vulkan/wsi/wayland: fix acquire_next_image to report timeouts properly
The Vulkan Specification states about possible return values from
vkAcquireNextImageKHR:

 * VK_NOT_READY is returned if timeout is zero and no image was
   available.
 * VK_TIMEOUT is returned if timeout is greater than zero and less than
   UINT64_MAX, and no image beae available within the time allowed.

That is, if info->timeout is larger than zero, the function must return
VK_TIMEOUT instead of VK_NOT_READY if no image became available before
the timeout elapsed.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21190>
2023-02-10 11:32:54 +00:00
Samuel Pitoiset 75ccf7c003 radv/ci: bump the number of runners to 3 for vkcts-navi21-valve
RADV_PERFTEST=gpl increased execution time, so let's try with a 3d
runner.

dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
seems reliably fixed now for some reasons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21214>
2023-02-10 11:06:54 +01:00
Samuel Pitoiset 6533709d10 radv/ci: set RADV_PERFTEST=GPL for all VKCTS jobs
The Vulkan CTS version in Mesa CI is so old that a bunch of tests
are broken, but it's expected.

This runs +283939 tests and the overall VKCTS execution time increased
from ~23 minutes to ~26 minutes (+~13%) on my Threadripper 1950X.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21214>
2023-02-10 11:06:54 +01:00
Pavel Ondračka 94eff7ccd8 nir: shrink phi nodes in nir_opt_shrink_vectors
While this change helps with few shaders, the main benefit is
that it allows to unroll loops comming from nine+ttn on vec4
backends. D3D9 REP ... ENDREP type loops are unrolled now already,
LOOP ... ENDLOOP need some nine changes that will come later.

r300 RV530 shader-db:
total instructions in shared programs: 132481 -> 132344 (-0.10%)
instructions in affected programs: 3532 -> 3395 (-3.88%)
helped: 13
HURT: 0

total temps in shared programs: 16961 -> 16957 (-0.02%)
temps in affected programs: 88 -> 84 (-4.55%)
helped: 4
HURT: 0

Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8102
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7222

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21038>
2023-02-10 09:06:25 +00:00