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Author SHA1 Message Date
Job Noorman d4d9cbdbef mailmap,bin/people.csv: fix my preferred email address 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36063>
 2025-07-11 12:04:08 +00:00
Mike Blumenkrantz de65a5ebac zink: fix fb attachment usage setting 
usage should always be set after barriers to improve reordering

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz 919ad8c08d zink: always emit fb attachment sync 
the sync functions should be smart enough by now to figure this out

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz 485b520cf2 zink: fix qbo sync 
this shouldn't be using bespoke handling to avoid sync

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13434

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz d6e89787ed zink: always create gfx shader objects with 5 descriptor layouts 
these are separate shader objects

fixes VUID-vkCmdDraw*-None-08879

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz 39f45f2a04 zink: double-check descriptor layout creation before adding to cache 
this can race against the background compile thread, so ensure that
no collisions happen

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz 033aa3560e zink: tighten up same-batch sync 
for a resource usage sequence like:
* TRANSFER_WRITE
* SHADER_READ
* TRANSFER_READ

the previous code would only synchronize SHADER_READ, which meant the
following TRANSFER_READ was subject to RaW hazards

instead, accumulate read accesses and emit new read sync when necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz efac6228b9 zink: unify setting general access flags in sync 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:10 +00:00
Mike Blumenkrantz 342313b145 zink: remove duplicate setting of last_write in image sync 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36057>
 2025-07-11 11:20:09 +00:00
Juan A. Suarez Romero cb22616f18 docs/features: GL_ARB_timer_query implemented for v3d 
This extension is implemented for v3d, but we forgot to update the
documentation.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36042>
 2025-07-11 08:03:45 +00:00
Samuel Pitoiset fa23a50322 radv: simplify creating descriptor sets with variable desciptor count 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36044>
 2025-07-11 06:04:41 +00:00
Samuel Pitoiset b7f4e344bc radv: fix the maximum variable descriptor count with inline uniform blocks 
It must not be larger than maxInlineUniformBlockSize.

Fixes recent VKCTS
dEQP-VK.api.maintenance3_check.support_count_inline_uniform_block*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36044>
 2025-07-11 06:04:41 +00:00
Samuel Pitoiset 36879c4f99 radv: fix indexing with variable descriptor count 
The Vulkan spec says:
    "If bindingCount is zero or if this structure is not included in
     the pNext chain, the VkDescriptorBindingFlags for each descriptor
     set layout binding is considered to be zero. Otherwise, the
     descriptor set layout binding at
     VkDescriptorSetLayoutCreateInfo::pBindings[i] uses the flags in
     pBindingFlags[i]."

Fixes recent VKCTS dEQP-VK.api.maintenance3_check.*.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13503
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36044>
 2025-07-11 06:04:40 +00:00
Samuel Pitoiset 01fccec1dc ac/descriptors,radv: move the nbc view param to the gfx10 union 
This is only GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36043>
 2025-07-11 05:46:50 +00:00
Samuel Pitoiset 36e4b52e9f radv: do not perform a per-pixel copy for BCn formats with mips on GFX12+ 
This is unnecessary because GFX12 isn't affected by this clamping issue
when NO_EDGE_CLAMP is correctly configured.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36043>
 2025-07-11 05:46:50 +00:00
Qiang Yu 88c79a13b9 ac,radv: move nir_load_ring_mesh_scratch_offset_amd to ac 
To be shared with radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 5ddbd8c83b ac,radv: move mesh scratch ring constants to ac 
To be shared with radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 78fed5fc13 ac,radv: move nir_load_task_ring_entry_amd to ac 
To be shared with radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 25897f0692 nir/recompute_io_bases: fix for per primitive IO 
It does not handle per primitive output and count
per primitive input.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 35e3f4ee92 nir: fix PRIMITIVE_INDICES mistreated as varying 
It's a sysval in mesh shader, but it share the same
slot number with VARYING_SLOT_TESS_LEVEL_INNER.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 1dbe7b65a1 radv: change mesh shader gs_vgpr_comp_cnt for gfx11 
It should always be 0, but now it's set to be 1 when gfx11
which allocate one unused VGPR.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 79ecca962a ac: parse ib for mesh shader dispatch packets 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 5c92fe45a1 radeonsi: support more than 64 options for AMD_DEBUG 
As we are going to add more debug options for mesh shader,
but now AMD_DEBUG options are full (=64).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu d9df597042 ac,radv: move mesh_fast_launch_2 to ac 
To be shared with radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu 09e6bc90ee radeonsi: fix gfx11 ngg shader emit 
Cc: mesa-stable
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:51 +00:00
Qiang Yu d0f76c4cd4 radeonsi: use mask for uses_bindless_samplers/images 
For simpler code and mesh shader support which need to
distinguish vertex and mesh pipeline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:50 +00:00
Qiang Yu b337e60a6f radeonsi: check render feedback only for fragment shader 
We set need_check_render_feedback for fragment shader only:
  69ad0fc61e ("radeonsi: only set need_check_render_feedback if binding textures for PS")

This helps adding mesh shader to not involve other geometry
stages so we can do it in either vertex or mesh pipeline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:50 +00:00
Qiang Yu aa7032ae83 mesa: remove gl_program.Target 
We are going to add mesh shader support, but there's
no GL_MESH_PROGRAM_EXT. Use shader stages instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:50 +00:00
Qiang Yu 2f5ff9788a Revert "gallium: add drawid_offset to draw_mesh_tasks interface" 
This reverts commit 27cd4b061c.

It's always 0.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:50 +00:00
Qiang Yu 2721283009 mesa: do not assume geometry shader when init 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:50 +00:00
Qiang Yu 0a4569fc92 gallium: remove ir arg from pipe_screen.get_compiler_options 
It's always PIPE_SHADER_IR_NIR.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35931>
 2025-07-11 02:25:50 +00:00
Timothy Arceri bda89200ce glsl: fix reuse of deref 
We can't reuse the deref or validation will get mad at us.

Fixes: 3da4b5eaa5 ("glsl: always copy bindless sampler packing constructors to a temp")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13464

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36038>
 2025-07-10 23:56:05 +00:00
Sagar Ghuge e761c45390 anv: Set TG size based on number of threads 
Series shows improvement on
TotalWarPharaoh-trace-dx11-1440p-ultra-n=2080 title by 0.96% (not a lot
but still it's improvement, so will take that.)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
Sagar Ghuge 5f1f67358c blorp: Set TG size based on number of threads 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
Sagar Ghuge 9b5149cb74 iris: Set TG size based on number of threads 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
Sagar Ghuge 0c4e1c9efc intel/common: Add helper for compute thread group dispatch size 
The recommended settings is just a guidance and not a programming
requirement as per the Bspec.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35904>
 2025-07-10 22:08:36 +00:00
Mary Guillemard b89bf4b79b nvk: Do not ignore contiguous in nvk_heap_init 
It was previously hardcoded since the switch to nvk_mem_arena.

Fixes: 9e52e296f7 ("nvk/heap: Use an nvk_mem_arena")
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36059>
 2025-07-10 21:18:04 +00:00
José Roberto de Souza 59019a05f6 anv: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers 
It was only added to indirect compute walkers while HSD don't say
anything about this optimization be specific to indirect compute
walkers.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36058>
 2025-07-10 20:54:30 +00:00
José Roberto de Souza aea519cbc2 intel/blorp: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers 
It was only added to indirect compute walkers while HSD don't say
anything about this optimization be specific to indirect compute
walkers.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36058>
 2025-07-10 20:54:30 +00:00
José Roberto de Souza 06997a42a3 iris: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers 
It was only added to indirect compute walkers while HSD don't say
anything about this optimization be specific to indirect compute
walkers.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36058>
 2025-07-10 20:54:30 +00:00
Emma Anholt 166b8b5774 ir3: Clarify a bit of the CS threadsize logic. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:28 +00:00
Emma Anholt 5c0c3a20dd ir3: Prioritize max waves over doubling threadsize for non-fp16 shaders. 
Improves average FPS across a set of 63 android and GL-with-zink traces by
1.9% (+/- 0.1%).  If we assume that SpaceEngine (most-improved traces by a
significant margin) is just an outlier, it still shows a .4% improvement.

Closes: #12747
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:28 +00:00
Emma Anholt 963e9ae770 ir3: Dump max_waves and double_threadsize with shader native code. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:28 +00:00
Emma Anholt 37333c67b1 ir3: Consider double_threadsize in the shader's sha1. 
It's a feature of the compiled shader that affects how it executes, but
it's not present in the binary itself.  Needed for debug tooling looking
into the effects of double_threadsize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:28 +00:00
Emma Anholt 707c97f634 tu: Add tracepoints around draws, with shader sha1s. 
Like for CSes, this lets you associate draw call times with the associated
shaders for pinpointing which pipelines are the most expensive.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:27 +00:00
Emma Anholt cf0828debb tu: Include the CS binary sha1 in CS dispatch tracepoints. 
This will help correlate from CS draw times back to the CS shader binaries
for analysis.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:27 +00:00
Emma Anholt e58f39fe2c ir3: Store the sha1 string of the compiled shader in the shader info. 
I want to use this for matching shaders to tracepoints, but you don't know
at compile time if the tracepoint will be enabled.  So we just always save
it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35759>
 2025-07-10 20:00:26 +00:00
Alyssa Rosenzweig 329413992e nir/lower_tex: revert "optimize LOD bias lower for txl" 
This reverts commit f853d285ef.

Failing a GL CTS test
https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/5866 .. apparently I ran
VK CTS but not GL CTS on that MR. Oops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35949>
 2025-07-10 15:00:28 -04:00
Alyssa Rosenzweig 9385ea1bf0 asahi: fix disasm of large shaders 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35949>
 2025-07-10 14:55:18 -04:00
Alyssa Rosenzweig 0bd1cd3230 agx: fix incorrect 16-bit promotions with comparisons 
hardware seems to sign extend with a signed comparison, which I guess is
reasonable! so our logic was busted if we had a zero-extend source with a signed
comparison. this broke someone's OpenCL app, and could probably be hit from
GLES/Vulkan too...

on fossil-db, only parallel-rdp affected:

Totals from 312 (0.58% of 53701) affected shaders:
Instrs: 404772 -> 405697 (+0.23%); split: -0.01%, +0.24%
CodeSize: 2863314 -> 2868998 (+0.20%); split: -0.01%, +0.21%
Spills: 40239 -> 40286 (+0.12%); split: -0.02%, +0.14%
Fills: 33763 -> 33810 (+0.14%); split: -0.03%, +0.17%
ALU: 290757 -> 291071 (+0.11%); split: -0.02%, +0.13%
FSCIB: 261844 -> 262652 (+0.31%); split: -0.02%, +0.33%
IC: 230312 -> 230336 (+0.01%); split: -0.01%, +0.02%
GPRs: 24656 -> 24648 (-0.03%); split: -0.05%, +0.02%

Reported-by: RowanG
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35949>
 2025-07-10 14:55:18 -04:00