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Lucas Stach ce124146e5 etnaviv: drop unused member PE_RT_COLOR_ADDR from compile framebuffer state 
Those relocs were never used.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35406>
 2025-06-13 18:44:34 +00:00
Lucas Stach e5c77d3367 etnaviv: add screen spec bit for PE multitiling 
There are a lot of places scattered through the driver where we check
if the GPU has more than a single pixel pipe and whether the single
buffer feature is supported. All of them are trying to work out if we
need to use multitiling for the PE render targets. Add a screen spec
flag to store the result of both checks and use it where appropriate.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35406>
 2025-06-13 18:44:33 +00:00
Job Noorman e31b1b649c ir3: optimize more before opt_preamble 
This prevents hoisting values to the preamble that might still get
optimized (away). This especially has a huge impact on binning variants
because many of their outputs got removed but we never optimized after
that.

fossildb stats:

Totals:
MaxWaves: 2765084 -> 2770308 (+0.19%); split: +0.19%, -0.00%
Instrs: 56289002 -> 56226045 (-0.11%); split: -0.13%, +0.02%
CodeSize: 118071672 -> 116551008 (-1.29%); split: -1.29%, +0.00%
NOPs: 9491112 -> 9477190 (-0.15%); split: -0.25%, +0.11%
MOVs: 1790085 -> 1789548 (-0.03%); split: -0.22%, +0.19%
Full: 2156693 -> 2140043 (-0.77%); split: -0.77%, +0.00%
(ss): 1329812 -> 1326394 (-0.26%); split: -0.66%, +0.40%
(sy): 686396 -> 686244 (-0.02%); split: -0.17%, +0.15%
(ss)-stall: 4995295 -> 4993233 (-0.04%); split: -0.69%, +0.65%
(sy)-stall: 19828966 -> 19833863 (+0.02%); split: -0.32%, +0.34%
STPs: 36271 -> 33249 (-8.33%)
LDPs: 45794 -> 42537 (-7.11%)
Preamble Instrs: 14467846 -> 13645555 (-5.68%); split: -5.69%, +0.01%
Early Preamble: 129346 -> 134346 (+3.87%); split: +3.89%, -0.02%
Cat0: 10450369 -> 10436616 (-0.13%); split: -0.23%, +0.10%
Cat1: 2787946 -> 2787085 (-0.03%); split: -0.15%, +0.12%
Cat2: 21265787 -> 21251803 (-0.07%); split: -0.07%, +0.01%
Cat3: 16207098 -> 16178995 (-0.17%); split: -0.17%, +0.00%
Cat5: 1596677 -> 1596707 (+0.00%)
Cat6: 854011 -> 848522 (-0.64%)
Cat7: 1597849 -> 1597052 (-0.05%); split: -0.13%, +0.08%

Totals from 22836 (11.41% of 200220) affected shaders:
MaxWaves: 335882 -> 341106 (+1.56%); split: +1.56%, -0.01%
Instrs: 6019621 -> 5956664 (-1.05%); split: -1.23%, +0.18%
CodeSize: 14192546 -> 12671882 (-10.71%); split: -10.74%, +0.03%
NOPs: 1107562 -> 1093640 (-1.26%); split: -2.18%, +0.92%
MOVs: 270465 -> 269928 (-0.20%); split: -1.43%, +1.23%
Full: 257820 -> 241170 (-6.46%); split: -6.47%, +0.01%
(ss): 156869 -> 153451 (-2.18%); split: -5.59%, +3.41%
(sy): 80161 -> 80009 (-0.19%); split: -1.46%, +1.27%
(ss)-stall: 573278 -> 571216 (-0.36%); split: -6.01%, +5.65%
(sy)-stall: 3537926 -> 3542823 (+0.14%); split: -1.78%, +1.92%
STPs: 30563 -> 27541 (-9.89%)
LDPs: 37112 -> 33855 (-8.78%)
Preamble Instrs: 2440099 -> 1617808 (-33.70%); split: -33.76%, +0.06%
Early Preamble: 9060 -> 14060 (+55.19%); split: +55.50%, -0.31%
Cat0: 1215965 -> 1202212 (-1.13%); split: -2.00%, +0.87%
Cat1: 475910 -> 475049 (-0.18%); split: -0.90%, +0.72%
Cat2: 1940479 -> 1926495 (-0.72%); split: -0.81%, +0.09%
Cat3: 1680902 -> 1652799 (-1.67%); split: -1.68%, +0.01%
Cat5: 151246 -> 151276 (+0.02%)
Cat6: 269190 -> 263701 (-2.04%)
Cat7: 174584 -> 173787 (-0.46%); split: -1.20%, +0.75%

Preamble improvements are even bigger on shaderdb:

total dwords in shared programs: 8800204 -> 8400960 (-4.54%)
dwords in affected programs: 1008384 -> 609140 (-39.59%)
helped: 3385
HURT: 14
helped stats (abs) min: 2 max: 1762 x̄: 118.02 x̃: 32
helped stats (rel) min: 0.21% max: 90.17% x̄: 32.93% x̃: 31.25%
HURT stats (abs)   min: 2 max: 32 x̄: 18.43 x̃: 26
HURT stats (rel)   min: 0.39% max: 16.67% x̄: 9.09% x̃: 13.13%
95% mean confidence interval for dwords value: -125.03 -109.88
95% mean confidence interval for dwords %-change: -33.46% -32.06%
Dwords are helped.

total preamble-inst in shared programs: 1274769 -> 1063479 (-16.57%)
preamble-inst in affected programs: 323660 -> 112370 (-65.28%)
helped: 3819
HURT: 5
helped stats (abs) min: 1 max: 1000 x̄: 55.33 x̃: 13
helped stats (rel) min: 0.61% max: 100.00% x̄: 53.55% x̃: 53.85%
HURT stats (abs)   min: 1 max: 9 x̄: 2.60 x̃: 1
HURT stats (rel)   min: 3.23% max: 6.34% x̄: 4.04% x̃: 3.70%
95% mean confidence interval for preamble-inst value: -58.84 -51.67
95% mean confidence interval for preamble-inst %-change: -54.22% -52.73%
Preamble-inst are helped.

total early-preamble in shared programs: 31297 -> 32057 (2.43%)
early-preamble in affected programs: 20 -> 780 (3800.00%)
helped: 780
HURT: 20
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.00% max: 0.00% x̄: 0.00% x̃: 0.00%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for early-preamble value: 0.93 0.97
95% mean confidence interval for early-preamble %-change: -3.58% -1.42%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34311>
 2025-06-13 16:12:01 +00:00
Job Noorman fca143946e ir3/lower_io_offsets: set progress when scalarizing UAV loads 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 91f19bcbe0 ("ir3: Plumb through two-dimensional UAV loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34311>
 2025-06-13 16:12:00 +00:00
Job Noorman 97dd831a07 ir3: don't vectorize 8bit SSBO accesses 
We already scalarize them but they might get vectorized again when
running the optimize loop before the intrinsics get turned into the
ir3-specific ones.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34311>
 2025-06-13 16:12:00 +00:00
Derek Foreman 07881b085e vulkan: Enable PresentWait2 on many physical devices 
PresentWait2 should be possible on any physical device, as it adds a
surface capability query that depends on common wsi code.

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
 2025-06-13 15:52:02 +00:00
Derek Foreman 074ab1db29 wsi/x11: add support for PresentWait2 
It's the same as PresentWait here, and always available.

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
 2025-06-13 15:52:02 +00:00
Derek Foreman 9a1a34836d wsi/display: Add support for PresentWait2 
It's really just the same as PresentWait here, and always available.

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
 2025-06-13 15:52:02 +00:00
Derek Foreman 3023f31cad wsi/wayland: Add support for PresentWait2 
Support PresentWait2 on any compositor that provides presentation feedback
protocol.

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
 2025-06-13 15:52:02 +00:00
Derek Foreman bf285c3be9 vulkan/wsi: Add basic support for PresentWait2 
Add common code for PresentWait2.

Unlike PresentWait, PresentWait2 is exposed by a surface capability.

On Wayland, PresentWait (and PresentWait2) require the presentation-time
extension to be available for a proper implementation, but not all
compositors support this. PresentWait would either have to be exposed
nowhere, or have weird/complicated fallback paths to try to enable it
on systems where presentation-time is unavailable.

Since PresentWait2 has a surface capability, we can simply not expose it
on Wayland when present-time is unavailable instead of always having to
have a less compliant fallback path.

PresentWait2 also explicitly forbids waiting on an ID that hasn't been
queued for presentation, so we don't need to handle that weird case.

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
 2025-06-13 15:52:02 +00:00
Job Noorman 29eb9ec7b7 Revert "ir3: optimize SSBO offset shifts for nir_opt_offsets" 
This reverts commit 57ea689273.

This optimization is only sound when the operands of iadd are unsigned.
It turns out this is not always the case.

While the particular failure I was seeing was fixed by changing the
unsigned shifts to signed ones, I don't believe this is sound either. So
it's better to disable it for now until we find a better solution.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 57ea689273 ("ir3: optimize SSBO offset shifts for nir_opt_offsets")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34324>
 2025-06-13 15:21:29 +00:00
Ville Syrjälä 3bd85064d4 iris: Don't use CCS_CC modifiers with INTEL_DEBUG=nofc 
Don't use the CCS_CC modifiers when fast clears are disabled
through INTEL_DEBUG=nofc. anv already behaves this way.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35417>
 2025-06-13 14:47:55 +00:00
Samuel Pitoiset 3c3684f4d4 radv: fix a compilation warning with Clang in radv_get_depth_clamp_mode() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35508>
 2025-06-13 14:31:22 +00:00
Lionel Landwerlin 854298e033 docs/features: update anv support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35426>
 2025-06-13 17:25:59 +03:00
Rhys Perry a905ff3d54 meson: add dep_llvm to radv_tests 
It seems this will try to link to LLVM because libvulkan_radeon links to
LLVM. Without the dep_llvm and with the GCC linker (instead of mold), this
will fail if you use a custom built LLVM and it can't find the shared object.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35495>
 2025-06-13 11:29:31 +00:00
Erik Faye-Lund 1145cac490 docs/features: mark vk 1.3 as complete on panvk/v10+ 
This already landed upstream, I just forgot to update this file.

While we're at it, update the vk 1.2-entry to only list V10+, to match
reality.

Fixes: 8ec846407d ("panvk: expose vulkan 1.3 support")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35513>
 2025-06-13 13:13:43 +02:00
Erik Faye-Lund 8ec846407d panvk: expose vulkan 1.3 support 
vulkanMemoryModel was the last required feature we needed to expose
Vulkan 1.3, so let's enable it!

Reviewed-by: Caterina Shablia <caterina.shablia@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35502>
 2025-06-13 12:05:28 +02:00
Erik Faye-Lund 8426973ad6 panvk: enable KHR_vulkan_memory_model 
We have all the pieces lined up now, so let's enable the memory model
extension.

Reviewed-by: Caterina Shablia <caterina.shablia@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35502>
 2025-06-13 12:05:25 +02:00
Erik Faye-Lund b3e18a606f panvk: optimize barriers 
It seems like a good idea to optimize barriers, so let's do the same
thing as most other drivers do.

Reviewed-by: Caterina Shablia <caterina.shablia@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35502>
 2025-06-13 12:05:04 +02:00
Erik Faye-Lund 6c17915fda pan/bi: handle barriers with NONE scope 
NONE-barriers also needs scheduling barriers, because otherwise we can
end up with memory loads and stores being reordered during scheduling.

Reviewed-by: Caterina Shablia <caterina.shablia@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35502>
 2025-06-13 12:05:03 +02:00
Erik Faye-Lund 18893a250f pan/bi: rework memory barriers 
The MEMORY_BARRIER instruction has some issues, where we end up
dead-code eliminating it before it gets to do what it's supposed to do.

But even if we fix that, we have issues where we can end up inserting
flow control into it, which isn't going to work because we have nothing
to emit here either.

So let's rework this to a special-cased NOP instruction, which is marked
as a scheduling barrier. The beneft here is that NOPs are already properly
handled when it comes to flow control.

Note that this isn't perfect either; this only prevents memory operations
from crossing the scheduling barrier. We should really prevent any
operation with observable side effects from crossing the barrier. This
includes things like reading clocks etc.

But that's a larger change, and it's a step in the right direction to get
this to no longer be dead-code eliminated. So let's put this band-aid on
for now.

Fixes: f77a50e45e ("pan/bi: add a MEMORY_BARRIER pseudo-instruction")
Reviewed-by: Caterina Shablia <caterina.shablia@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35502>
 2025-06-13 12:05:02 +02:00
Christian Gmeiner 31e4e38f7d crocus: Don't use deprecated NIR_PASS_V macro 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35503>
 2025-06-13 09:08:21 +00:00
Christian Gmeiner c80d75afe5 crocus: Return progress for crocus_lower_storage_image_derefs(..) 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35503>
 2025-06-13 09:08:21 +00:00
Samuel Pitoiset 161f27e206 radv: enable shaderImageFloat32AtomicAdd on GFX12 with ACO 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35493>
 2025-06-13 08:47:59 +00:00
Samuel Pitoiset d23de4918e aco: add support for image f32 atomic add 
It's supported on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35493>
 2025-06-13 08:47:59 +00:00
Samuel Pitoiset c5bf1caf17 radv: enable shaderBufferFloat32AtomicMinMax on GFX12 
This is supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35493>
 2025-06-13 08:47:59 +00:00
Olivia Lee d0b353018f panvk: Add tests for ls tracking in cs_maybe 
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35460>
 2025-06-13 08:28:30 +00:00
Ludvig Lindau 3778b22268 panvk: Fix ls_tracker usage in cs_maybe 
Currently a cs_maybe block affects the ls_tracker of a command stream
even if the cs_maybe block is later replaced by NOP instructions. This
can lead to missing WAIT instructions in the command stream.

* Add a WAIT at the end of the cs_maybe block if the block has changed
 the ls_tracker state
* At the end of a cs_maybe block, restore the ls_tracker state to what
 it was before the block

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13259
Fixes: 885805560f ("panvk/csf: fix case where vk_meta is used before PROVOKING_VERTEX_MODE_LAST")
Tested-By: Alexandre ARNOUD <aarnoud@me.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35460>
 2025-06-13 08:28:30 +00:00
Samuel Pitoiset 8dd496955d radv: advertise VK_KHR_unified_image_layouts on GFX11+ 
On GFX12, everything is compressed with DCC and it's completely
transparent to the userspace driver.

On GFX11-GFX11.5, DCC can compress everything with GENERAL and FMASK
has been merged with DCC.

On GFX10-GFX10.3, MSAA through FMASK can't be compressed with GENERAL
and this will hurt performance.

On GFX6-9, DCC can't be supported with GENERAL because no DCC stores,
so this will destroy performance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35424>
 2025-06-13 08:12:04 +00:00
Samuel Pitoiset a3fa8eed4c radv: implement VK_KHR_unified_image_layouts 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35424>
 2025-06-13 08:12:04 +00:00
Samuel Pitoiset eeabce93b6 radv: use constants for different descriptor sizes 
Instead of magic values everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35428>
 2025-06-13 07:53:04 +00:00
Samuel Pitoiset 939b66a798 radv: remove unused 96-bit memcpy for image descriptors 
This can only be 32, 64 or 80 for combined image/sampler.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35428>
 2025-06-13 07:53:04 +00:00
Samuel Pitoiset 6b604ff60f radv: cleanup redundant switch cases in radv_GetDescriptorEXT() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35428>
 2025-06-13 07:53:04 +00:00
Samuel Pitoiset 63f8b8ce6d radv/nir: adjust a comment about inlining immutable samplers 
That (broken) optimization has been removed few weeks ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35428>
 2025-06-13 07:53:04 +00:00
Samuel Pitoiset d5da47f831 radv: advertise VK_KHR_maintenance9 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35423>
 2025-06-13 07:33:03 +00:00
Samuel Pitoiset 99fb1a9bd7 radv/nir: lower unassigned vertex attributes to (0,0,0,0) 
The spec allows both 0,0,0,0 and 0,0,0,1. Returning all zeroes makes it
consistent with vertex prologs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35423>
 2025-06-13 07:33:03 +00:00
Samuel Pitoiset 4e46cabb75 radv: add support for VK_QUERY_POOL_CREATE_RESET_BIT_KHR 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35423>
 2025-06-13 07:33:03 +00:00
Karol Herbst 4ff66b4343 ac/llvm: fix bitfield ops 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35423>
 2025-06-13 07:33:03 +00:00
Samuel Pitoiset 358addb78d radv: unset radv_lower_terminate_to_discard=true for Indiana Jones 
This game bug has been fixed since.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35023>
 2025-06-13 06:43:47 +00:00
Samuel Pitoiset 36c0c1e857 Revert "radv,driconf: Add radv_force_64k_sparse_alignment config" 
This reverts commit e32a90b57c.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35023>
 2025-06-13 06:43:47 +00:00
Samuel Pitoiset aed7045bc9 radv: unset radv_force_64k_sparse_alignment for DOOM: The Dark Ages 
Looks like this has been fixed by the game.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35023>
 2025-06-13 06:43:47 +00:00
Samuel Pitoiset 817f7f1bb2 radv: remove radv_disable_dedicated_sparse_queue completely 
This drirc workaround is probably not useful since RADV allows SPARSE
on all queues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35023>
 2025-06-13 06:43:47 +00:00
Samuel Pitoiset 4cc9bb4532 radv: unset radv_disable_dedicated_sparse_queue for Bethesda Games 
This shouldn't be needed anymore since f58630f07c ("radv: Always
allow sparse on normal GFX/COMPUTE/DMA queues."). These games were
always assuming that GFX queue supported sparse which wasn't correct
with the dedicated sparse queue.

List of games that are concerned:
- DOOM Eternal
- Indiana Jones: The Great Circle
- DOOM: The Dark Ages

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35023>
 2025-06-13 06:43:46 +00:00
Samuel Pitoiset 7f7ed18929 radv: fix 3-plane formats with descriptor buffers 
Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35455>
 2025-06-13 06:27:26 +00:00
Samuel Pitoiset 22e06d65d7 radv: make sure to zero-initialize image view descriptors 
This prevents a regression from the next commit which would write
garbage for combined image+sampler descriptors and that might break
capture&replay.

It seems also more robust to write zeroes than garbage overall.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35455>
 2025-06-13 06:27:25 +00:00
Tapani Pälli 6e57f3738d drirc: toggle on intel_storage_cache_policy_wt for tlou2 
Fixes rendering issues seen in the game.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12948
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35486>
 2025-06-13 06:04:22 +00:00
Hyunjun Ko 0d3ffd8275 anv: enable the KHR_video_decode_vp9 extension 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
 2025-06-13 04:51:51 +00:00
Hyunjun Ko 314de7af06 anv: Initial support for VP9 decoding 
Helped from: Stéphane Cerveau <scerveau@igalia.com>
- Fix crash when segmentation is unavailable
- Set 8x8 to minCodedExtent
- Fix typo for GOLDEN and ALTREF scale factor

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
 2025-06-13 04:51:51 +00:00
Hyunjun Ko 0689e3d873 anv: add default vp9 tables from FFMpeg and intel-vaapi-driver 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
 2025-06-13 04:51:51 +00:00
Hyunjun Ko 213ca2ac9a intel/genxml: fix HCP_VP9 commands 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
 2025-06-13 04:51:51 +00:00