cd343fb9ac
intel/brw: Add support for fcsel opcodes
...
Don't enable nir_opt_algebraic to generate these opcodes yet.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095 >
2024-05-14 01:28:20 +00:00
d51ad9f4e0
intel/brw: Use fs_inst::resize_sources in brw_fs_opt_algebraic
...
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095 >
2024-05-14 01:28:20 +00:00
11c6b6c102
intel/elk: Remove dsign optimization
...
This bit from the comment should have been a big red flag:
There are currently zero instances of fsign(double(x))*IMM in
shader-db or any test suite, so it is hard to care at this time.
The implementation of that path was incorrect. The XOR instructions
should be predicated like the OR instruction in the non-multiplication
path. As a result, dsign(zero_value) * x will not produce the correct
result.
Instead of fixing this code that is never exercised by anything, replace
it with the simple lowering in NIR.
Ironically, the vec4 implementation is correct. The odds of encountering
an application that is performace limited by dsign performance in vertex
processing stages on Ivy Bridge or Haswell is infinitesimal.
No shader-db changes on any Intel platform.
v2: Delete 's' in emit_fsign as it is now unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org > [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095 >
2024-05-14 01:28:20 +00:00
ded8690336
intel/brw: Remove dsign optimization
...
This bit from the comment should have been a big red flag:
There are currently zero instances of fsign(double(x))*IMM in
shader-db or any test suite, so it is hard to care at this time.
The implementation of that path was incorrect. The XOR instructions
should be predicated like the OR instruction in the non-multiplication
path. As a result, dsign(zero_value) * x will not produce the correct
result.
Instead of fixing this code that is never exercised by anything, replace
it with the simple lowering in NIR.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095 >
2024-05-14 01:28:20 +00:00
b8dbd64267
intel/brw: Fix commas when dumping instructions
...
Some commas were being skipped, according to history as an attempt
to elide BAD_FILEs, but we still print them, so be consistent. Also
for instructions without any sources, the trailing comma was always
being printed. Fix that too.
Example of instruction output before the change
halt_target(8) (null):UD,
send(8) (mlen: 1) (EOT) (null):UD, 0u, 0u, g126:UD(null):UD NoMask
and after it
halt_target(8) (null):UD
send(8) (mlen: 1) (EOT) (null):UD, 0u, 0u, g126:UD, (null):UD NoMask
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29114 >
2024-05-11 02:17:57 +00:00
c9fe20fdf1
intel/brw: Use vNN instead of vgrfNN when printing instructions
...
Reduce the noise in the shader dump output.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29114 >
2024-05-11 02:17:56 +00:00
3a081106b0
intel/brw: Hide register pressure information in dumps
...
It was the default to show register pressure for each instruction,
but it gets in the way of cleaner diffs before/after an optimization pass.
Add INTEL_DEBUG=reg-pressure option to show it again.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29114 >
2024-05-11 02:17:56 +00:00
866b1245e9
intel/brw: Don't print IP as part of the dump
...
The sequential IP cause noise when diffing before/after a pass that
either add or remove instructions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29114 >
2024-05-11 02:17:56 +00:00
fd47f90d37
brw: drop dependency on libintel_common
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11136
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29128 >
2024-05-11 01:52:01 +00:00
36c043e2eb
intel: move debug identifier out of libintel_dev
...
The debug identifier is put into the captured buffers for error
capture. This helps us figure out what version of the driver people
are running when encountering a GPU hang. This identifier has the
git-sha1 + driver name.
libintel_dev is also a dependency of the compiler so any change to the
git-sha1 also triggers recompile which we want to avoid.
This changes moves the debug identifier to src/intel/common which
drivers already depend on, so the compiler is not affected anymore.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11136
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29128 >
2024-05-11 01:52:01 +00:00
d1c01e256d
brw: add more condition for reducing sampler simdness
...
Running
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor test
with Zink on Anv we run into an assert :
assert(inst->mlen <= MAX_SAMPLER_MESSAGE_SIZE * reg_unit(devinfo));
Turns out we've not covered all the cases in the SIMD lowering.
It's a bit of a shame to have both files reproduce the same logic.
Will try to think of a better way to extract the layout of the a send
message but that'll be a much bigger rework.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29118 >
2024-05-10 19:40:00 +00:00
90866bc58c
anv,hasvk: use common stype debug
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29009 >
2024-05-10 18:49:38 +00:00
69fc7ee622
intel/disasm: Fix cache load/store disassembly for URB messages
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28868 >
2024-05-09 19:45:18 +00:00
91b62e9868
anv: Use spirv_capabilities for the float64 shader
...
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Iván Briano <ivan.briano@intel.com >
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905 >
2024-05-09 01:14:23 +00:00
9d5b4a4ffd
intel/kernel: Use the new capabilities struct
...
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Iván Briano <ivan.briano@intel.com >
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905 >
2024-05-09 01:14:23 +00:00
ce2946ae0f
vulkan: Set SPIR-V caps from supported features
...
Any drivers which use vk_spirv_to_nir() now no longer need to build a
caps table manually.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Iván Briano <ivan.briano@intel.com >
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905 >
2024-05-09 01:14:23 +00:00
c1eaa03904
spirv: Drop the SubgroupUniformControlFlow check
...
It's just a vtn_fail_if() and there's no actual cap for it. It's not
really gaining us much to have the check.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Iván Briano <ivan.briano@intel.com >
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28905 >
2024-05-09 01:14:22 +00:00
28a0f98123
intel/tools: add README file
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594 >
2024-05-08 22:50:47 +00:00
bab52763f4
intel/hang_replay: fix batch address
...
Also capture all buffers so that we can compare replay run with the
original error state.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594 >
2024-05-08 22:50:47 +00:00
a9f1151de2
intel/hang_replay: use hw image param
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594 >
2024-05-08 22:50:47 +00:00
4d69870071
intel/hang_replay: use newer API of i915 execbuffer
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27594 >
2024-05-08 22:50:47 +00:00
665cad6408
anv: fix ycbcr plane indexing with indirect descriptors
...
We need to add the plane index to compute the address from which to
load the descriptor (anv_sampled_image_descriptor in this case).
This was likely broken before we added direct descriptor support so
that gets a stable backport.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11125
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29111 >
2024-05-08 21:51:49 +00:00
c225f89d34
anv: skip gfx push constants alloc optimization on gfx9/11
...
Always reallocate in cmd_buffer_flush_gfx_push_constants like was done
before the the optimization got introduced.
Fixes: 62d96a6546https://gitlab.freedesktop.org/mesa/mesa/-/issues/11064
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Tested-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28999 >
2024-05-08 17:21:26 +00:00
73188a4590
intel/perf: Add function to open perf stream
...
This will make easy to add Xe KMD support and reduce code duplication.
No changes in behavior are expected here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
d27dcb815e
intel/perf: Add and use a function to return platform OA format
...
The platform version check to return the OA format was duplicated
in a few places, so adding a function and dropping this duplication.
While at it, already making it future proof for Xe KMD support and
split i915 specific code to its own file.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
137021fbe0
hasvk: Free intel_perf_config when destroying physical device
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
a941ce746a
anv: Free intel_perf_config when destroying physical device
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
4b179e7bea
intel/ds: Nuke ralloc_ctx and ralloc_cfg
...
Now that perf config and context are freed we don't need this rallocs
contexts.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
6c3ebff569
intel/ds: Free perf config and context
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
2cecf3e8a8
intel/perf: Add intel_perf_free_context()
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
ebe8d2f9ea
intel/perf: Add intel_perf_free()
...
There was no function to free resources allocated in intel_perf_config
or it self.
Other callers will be added in separated patches.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
a9a53c914d
intel/perf: Store pointer intel_device_info to in intel_perf_config
...
This will reduce host memory usage a bit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29077 >
2024-05-07 21:44:34 +00:00
2d575034f2
hasvk: switch to use runtime physical device properties infrastructure
...
Remove the GPDP and GPDP2 entrypoints, and fill the properties
at device initialization time instead.
Move DRM master major/minor gathering before get_properties() and WSI
init, as the latter uses the results gathered by the former.
Reviewed-by: Julia Tatz <tatz.j@northeastern.edu >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27717 >
2024-05-07 08:45:18 +00:00
55967a411d
anv: Move completely over to common runtime GetPhysicalDeviceProperties2
...
The runtime grew support for VkPhysicalDevicePresentationPropertiesANDROID,
so we can use that now and get rid of anv_GetPhysicalDeviceProperties2.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27717 >
2024-05-07 08:45:17 +00:00
8c1cc405d3
anv: VK_EXT_legacy_vertex_attributes
...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29070 >
2024-05-07 08:16:20 +03:00
e32828f5fc
intel/compiler: Fix destination type for CMP/CMPN
...
For CMP/CMPN, use src0 type if destination is null otherwise get the
src0 type register with destination register size.
This fixes dEQP-VK.glsl.builtin_var.frontfacing.* tests cases on Xe2+.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28679 >
2024-05-06 21:46:18 +00:00
610a7c84c3
anv: move empty_vs_input to physical device
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057 >
2024-05-06 09:20:01 +00:00
725397759a
anv: move device initialization as the last step of vkCreateDevice
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057 >
2024-05-06 09:20:01 +00:00
63c4d24f7d
anv: avoid requirement to put flush_data as first field
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057 >
2024-05-06 09:20:01 +00:00
ae6d20815a
anv: fix leak of custom border colors
...
Inside a HAVE_VALGRIND section.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 4dad2a4a6frohan.garg@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057 >
2024-05-06 09:20:01 +00:00
e260b16b11
anv: fixup alloc failure handling in reserved_array_pool
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 806281f61frohan.garg@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29057 >
2024-05-06 09:20:01 +00:00
0fa17962d6
intel/elk: Fix optimize_extract_to_float for i2f of unsigned extract
...
Fixes fs-uint-to-float-of-extract-int8.shader_test and
fs-uint-to-float-of-extract-int16.shader_test added by piglit!883.
v2: Expand the comment explaining the potential problem. Suggested by
Caio.
Fixes: e6022281f2caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27891 >
2024-05-03 15:01:43 -07:00
fc2360167c
intel/brw: Avoid optimize_extract_to_float when it will just be undone later
...
v2: Add bspec quotation. Suggested by Caio. With better understand of
the restriction, only apply on DG2 and newer platforms.
shader-db:
DG2 and Meteor Lake had similar results. (DG2 shown)
total instructions in shared programs: 19659363 -> 19659360 (<.01%)
instructions in affected programs: 2484 -> 2481 (-0.12%)
helped: 6 / HURT: 1
total cycles in shared programs: 823445738 -> 823432524 (<.01%)
cycles in affected programs: 2619836 -> 2606622 (-0.50%)
helped: 48 / HURT: 63
fossil-db:
DG2 and Meteor Lake had similar results. (DG2 shown)
Totals:
Instrs: 154015863 -> 153987806 (-0.02%); split: -0.02%, +0.00%
Cycle count: 17552172994 -> 17562047866 (+0.06%); split: -0.13%, +0.19%
Spill count: 142124 -> 141544 (-0.41%); split: -0.54%, +0.13%
Fill count: 266803 -> 266046 (-0.28%); split: -0.38%, +0.09%
Scratch Memory Size: 10266624 -> 10271744 (+0.05%); split: -0.02%, +0.07%
Max live registers: 32592428 -> 32592393 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 5535944 -> 5535912 (-0.00%); split: +0.00%, -0.00%
Totals from 41887 (6.63% of 631367) affected shaders:
Instrs: 32971032 -> 32942975 (-0.09%); split: -0.10%, +0.01%
Cycle count: 3892086217 -> 3901961089 (+0.25%); split: -0.60%, +0.85%
Spill count: 105669 -> 105089 (-0.55%); split: -0.72%, +0.18%
Fill count: 206459 -> 205702 (-0.37%); split: -0.49%, +0.12%
Scratch Memory Size: 7766016 -> 7771136caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27891 >
2024-05-03 15:01:43 -07:00
bf5d82654a
intel/brw: Fix optimize_extract_to_float for i2f of unsigned extract
...
Fixes fs-uint-to-float-of-extract-int8.shader_test and
fs-uint-to-float-of-extract-int16.shader_test added by piglit!883.
No shader-db or fossil-db changes on any Intel platform.
v2: Expand the comment explaining the potential problem. Suggested by
Caio.
Fixes: 29ce110be6caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27891 >
2024-05-03 15:01:43 -07:00
8d983b3425
intel/nir: Set src_type on TCS quads workaround store_output
...
We weren't setting this and now it's validated, causing assert failures.
Fixes: 1632948a76https://gitlab.freedesktop.org/mesa/mesa/-/issues/11107
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29027 >
2024-05-02 13:58:21 -07:00
39c4de7e42
anv: Fix descriptor sampler offsets assignment
...
This seems to be a simple copy-paste mistake. It makes sense to or-assign
surface offsets because we clear the actual offset part with a mask first,
but sampler offsets should be just assigned instead.
Fixes: 7c76125dhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/10790
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29019 >
2024-05-02 14:49:37 +00:00
be518657b9
intel/perf: Change oa_format to uint64_t
...
Xe KMD will not provide a enum with formats, instead UMD needs set
a uint64_t with type, counter_sel, counter_size and bc_report for the
format.
So here changing from int to uint64_t, it do not causes any issues for
i915 and makes it ready for Xe KMD.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997 >
2024-05-02 14:25:41 +00:00
9cb4ff9b0e
intel/perf: Fix the error check of i915_add_config()
...
i915_add_config() returns 0 for error or a positive integer for success
but callers were checking for a negative number for errors.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997 >
2024-05-02 14:25:41 +00:00
a56dc30ba6
intel/perf: Remove i915_drm.h include from gen_perf.py
...
The generated file don't use any symbol in i915_drm.h
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997 >
2024-05-02 14:25:40 +00:00
14b890c797
intel/perf: Nuke platform_supported
...
Only set, never used.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28997 >
2024-05-02 14:25:40 +00:00
Ian Romanick