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Author SHA1 Message Date
Marek Olšák cab5b3861d radeonsi/gfx10: fix tessellation for the legacy pipeline 
ported from PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák a9bb566955 radeonsi: move some global shader cache flags to per-binary flags 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák 810846e157 radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache 
It could load an NGG shader when we want a legacy shader and vice versa.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Kenneth Graunke 6342d43ae9 iris: Delete dead prototype 2019-08-27 13:15:02 -07:00
Boris Brezillon 2734a4951e Revert "panfrost: Free all block/instruction objects before leaving midgard_compile_shader_nir()" 
This reverts commit 5882e0def9.

This commit causes a segfault.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
 2019-08-27 20:07:28 +02:00
Boris Brezillon 0142dcb990 panfrost: Make sure bundle.instructions[] contains valid instructions 
Add an assert() in schedule_bundle() to make sure all instruction
pointers in bundle.instructions[] are valid.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2019-08-27 16:50:52 +02:00
Boris Brezillon 5882e0def9 panfrost: Free all block/instruction objects before leaving midgard_compile_shader_nir() 
Right now we're leaking all block and instruction objects allocated by
the compiler. Let's clean things up before leaving
midgard_compile_shader_nir().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2019-08-27 16:50:52 +02:00
Boris Brezillon 3ac49f135a panfrost: Free the instruction object in mir_remove_instruction() 
To avoid memory leaks.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2019-08-27 16:50:52 +02:00
Eric Engestrom 239f7f1c0a scons: add support for MAJOR_IN_{MKDEV,SYSMACROS} 
src/gallium/winsys/svga/drm/vmw_screen.c: In function ‘vmw_dev_compare’:
src/gallium/winsys/svga/drm/vmw_screen.c:48:12: warning: implicit declaration of function ‘major’ [-Wimplicit-function-declaration]
   48 |    return (major(*(dev_t *)key1) == major(*(dev_t *)key2) &&
      |            ^~~~~
src/gallium/winsys/svga/drm/vmw_screen.c:49:12: warning: implicit declaration of function ‘minor’ [-Wimplicit-function-declaration]
   49 |            minor(*(dev_t *)key1) == minor(*(dev_t *)key2)) ? 0 : 1;
      |            ^~~~~

That file (and many others) already has the proper #include with their
respective guards, but scons wasn't defining them, resulting in implicit
functions being used instead (and an always-true check that's probably
breaking something down the line).

Note that I'm cheating a bit here because Scons doesn't seem to have
a clean way to detect the existence of major() et al. as functions or
macros, so I'm taking the shortcut of just detecting the presence of the
header and assuming its contents is what we expect.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
 2019-08-27 14:03:46 +01:00
Samuel Pitoiset 49f5ddd3ae radv: make use of has_ls_vgpr_init_bug 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-08-27 08:04:51 +02:00
Samuel Pitoiset fd54fc85aa ac: add has_ls_vgpr_init_bug to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:47 +02:00
Samuel Pitoiset 1bf2572dff ac: add has_msaa_sample_loc_bug to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:44 +02:00
Samuel Pitoiset 021feb1bf6 ac: add rbplus_allowed to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:41 +02:00
Samuel Pitoiset 20c5db02b5 ac: add has_tc_compat_zrange_bug to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:36 +02:00
Samuel Pitoiset b55919cf2a ac: add has_gfx9_scissor_bug to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:32 +02:00
Samuel Pitoiset 2b9c371575 ac: add cpdma_prefetch_writes_memory to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:29 +02:00
Samuel Pitoiset b027ad66d7 ac: add has_out_of_order_rast to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:26 +02:00
Samuel Pitoiset ed720af46d ac: add has_load_ctx_reg_pkt to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:22 +02:00
Samuel Pitoiset 63c0b89b8f ac: add has_rbplus to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:19 +02:00
Samuel Pitoiset 44a46c09de ac: add has_dcc_constant_encode to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:16 +02:00
Samuel Pitoiset c08401f035 ac: add has_distributed_tess to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:11 +02:00
Samuel Pitoiset d62d2840c4 ac: add has_clear_state to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:05 +02:00
Samuel Pitoiset af65f9431e ac: drop llvm8 from some load/store helpers 
Cleanup.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:00 +02:00
Dave Airlie e6eb444554 gallivm: fix appveyor build after images changes 2019-08-27 13:36:03 +10:00
Dave Airlie c501c2cef6 docs: add shader image extensions for llvmpipe 
v1.1: fix typo in llvmpipe name (ajax)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:25 +10:00
Dave Airlie b7468f7831 llvmpipe: enable ARB_shader_image_load_store 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:22 +10:00
Dave Airlie 6c2fa01b9c llvmpipe: flush on api memorybarrier. 
Until we have somewhere we can do better, just hit it with a hammer.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:16 +10:00
Dave Airlie b9bf236c71 gallivm: add memory barrier support 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:13 +10:00
Dave Airlie abfb633968 gallivm: add support for fences api on older llvm 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:10 +10:00
Dave Airlie 8b7295f281 llvmpipe: bind vertex/geometry shader images 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:06 +10:00
Dave Airlie 2909c654b0 llvmpipe: add fragment shader image support 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:04 +10:00
Dave Airlie dc2357070c draw: add vs/gs images support 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:30:01 +10:00
Dave Airlie ceb8d0ac5a gallivm: add image load/store/atomic support 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:58 +10:00
Dave Airlie 15f7688ac9 gallivm/tgsi: add image interface to tgsi builder 
This adds the callbacks for the driver/gallium binding for
image operations.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:55 +10:00
Dave Airlie b2be174be2 llvmpipe: introduce image jit type to fragment shader jit. 
This adds the image type to the fragment shader jit context

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:51 +10:00
Dave Airlie 039a2e3630 draw: add jit image type for vs/gs images. 
This introduces the jit image type into the jit interface
for vertex/geom shaders

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:49 +10:00
Dave Airlie 3c2c232059 llvmpipe: move the fragment shader variant key to dynamic length. 
This mirrors the vs/gs keys, and will be needed when adding images
support.

The const changes also mirror how the draw code work (as is needed
when we add images)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:42 +10:00
Dave Airlie d0381ea149 gallivm: add a basic image limit 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:39 +10:00
Dave Airlie cf84b46a1c llvmpipe: handle early test property. 
Also handle setting late for shaders that use stores

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:33 +10:00
Dave Airlie a1e8fcef47 gallivm: move first/last level jit texture members. 
This lets us create an image structure with the same basic
types as the texture one.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:31 +10:00
Dave Airlie e8a445d8b5 gallivm: handle helper invocation (v2) 
Just invert the exec_mask to get if this is a helper or not.

v2: get the bld mask (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:28 +10:00
Dave Airlie fb34369eb5 gallivm: make lp_build_float_to_r11g11b10 take a const src 
This allows using it with a const src later.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:25 +10:00
Dave Airlie a8ef6b5755 llvmpipe: refactor jit type creation 
This just cleans the code up so the texture/sampler type
creation can be reused.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:29:21 +10:00
Dave Airlie 1eda49cc3d gallivm: fix atomic compare-and-swap 
Not sure how I missed this before, but compswap was hitting an
assert here as it is it's own special case.

Fixes: b5ac381d8f ("gallivm: add buffer operations to the tgsi->llvm conversion.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2019-08-27 12:28:17 +10:00
Paulo Zanoni 848d5e444a intel/fs: grab fail_msg from v32 instead of v16 when v32->run_cs fails 
Looks like a copy/paste error. This patch prevents a segfault when
running the following on BDW:

    INTEL_DEBUG=no8,no16,do32 ./deqp-vk -n \
        dEQP-VK.subgroups.arithmetic.compute.subgroupmin_dvec4

For the curious, the message we're getting is:

    CS compile failed: Failure to register allocate.  Reduce number
    of live scalar values to avoid this.

Fixes: 864737ce6c ("i965/fs: Build 32-wide compute shader when needed.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
 2019-08-26 14:54:16 -07:00
Alyssa Rosenzweig c30116a2fa pan/midgard: Fix invert fusing with r26 
The invert wasn't applying (correctly) due to the issues addressed here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2019-08-26 13:43:04 -07:00
Alyssa Rosenzweig 75b6be2435 pan/midgard: Fold ssa_args into midgard_instruction 
This is just a bit of refactoring to simplify MIR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2019-08-26 13:43:04 -07:00
Eric Anholt 0309fb82ec gallium: Add the ASTC 3D formats. 
No driver implements them yet, but this is a long way toward gallium
having matching format enums for Mesa formats.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-26 19:44:00 +00:00
Eric Anholt 9d988f9291 gallium: Add block depth to the format utils. 
I decided not to update nblocks() with a depth arg as the callers
wouldn't be doing ASTC 3D.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-26 19:44:00 +00:00
Eric Anholt 530f424735 gallium: Add a block depth field to the u_formats table. 
To add ASTC 3D compression formats, we need to be able to express the
block depth.  While I'm touching every line, line up the columns of
the CSV again as they've drifted over time.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-26 19:44:00 +00:00