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Author SHA1 Message Date
Gert Wollny
ca270207bb r600/sfn: lower find_msb variants to find_msb_rev 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
 2021-03-22 15:19:46 +01:00
Gert Wollny
befda5ba1b r600/sfn: optimize comp+csel using fused ops 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
 2021-03-22 15:19:46 +01:00
Gert Wollny
195952786b r600/sfn: Add algebraic lowering for fsin and fcos 
* fsin and fcos require normalization of the input
* bitfield_insert requires an additional shift of the insert value

v2: drop bitfield_insert lowering code, it is already avaibable as
    compiler option (Rhys Perry)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
 2021-03-22 15:19:46 +01:00
Gert Wollny
318701b803 nir: Add r600 specific sin and cos variants 
r600 expect the input values to be normalited by divinding by 2 *PI, so
add an opcode to be able to lower this in nir.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
 2021-03-22 15:19:46 +01:00
Gert Wollny
0f5b3c37c5 nir: Add opcodes for fused comp + csel and optimizations 
Some backends, like r600 support a fused version of int and float compare
against zero and and csel. Adding these opcodes here makes it possible to
optimize this in nir.

v2: Add rules for float compare + csel

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
 2021-03-22 15:19:46 +01:00
Gert Wollny
a5747f8ab3 nir: add opcodes for *find_msb_rev and lowering 
Some hardware supports a version of find_msb where the bits are counted
starting at the high bit, and this needs some lowering to obtain the
value that is expected by *find_msb

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>
 2021-03-22 15:19:46 +01:00
Rhys Perry
28d116c889 radv: lower view_index to zero if multiview is disabled 
Apparently, gl_ViewIndex can be used if multiview is disabled.

See https://gitlab.freedesktop.org/mesa/mesa/-/issues/4446

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9718>
 2021-03-22 13:38:43 +00:00
Mike Blumenkrantz
92a5ea13fc zink: implement a global framebuffer cache 
this uses the same mechanics as surface caching, but it
also requires that surfaces keep refs of the framebuffers they're
attached to so that they can invalidate the fb object upon destruction,
as, similar to program objects, the fb objects are "owned" by their attachments

loosely based on patches by Antonio Caggiano

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>
 2021-03-22 08:49:26 -04:00
Mike Blumenkrantz
9b544c1fe7 zink: use a custom surface referencing function whenever unrefing a surface 
pipe_surface_reference uses surface->context, which is not reliable when sharing
surfaces between contexts. since a surface will never be destroyed outside of
zink if its context is dead, forcing surfaces to go directly to the screen object
prevents accessing dead contexts

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>
 2021-03-22 08:49:26 -04:00
Mike Blumenkrantz
a9ab5b4f16 zink: break out surface destroy function into a screen function 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>
 2021-03-22 08:49:26 -04:00
Mike Blumenkrantz
c56fe22064 zink: use surface references for fb attachments 
this guarantees the lifetimes of framebuffer surfaces

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>
 2021-03-22 08:49:26 -04:00
Mike Blumenkrantz
17ef151f62 zink: add explicit surface/bufferview batch-tracking functions 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>
 2021-03-22 08:49:26 -04:00
Mike Blumenkrantz
73fa8c2bdb zink: make fb ref func return bool on free 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>
 2021-03-22 08:49:26 -04:00
Iago Toral Quiroga
cbe24a0e9c broadcom/compiler: use nir_lower_undef_to_zero 
total instructions in shared programs: 13731663 -> 13721549 (-0.07%)
instructions in affected programs: 98242 -> 88128 (-10.29%)
helped: 191
HURT: 131
Instructions are helped.

total threads in shared programs: 412272 -> 412296 (<.01%)
threads in affected programs: 24 -> 48 (100.00%)
helped: 12
HURT: 0
Threads are helped.

total uniforms in shared programs: 3780693 -> 3779137 (-0.04%)
uniforms in affected programs: 10564 -> 9008 (-14.73%)
helped: 114
HURT: 7
Uniforms are helped.

total max-temps in shared programs: 2319942 -> 2319528 (-0.02%)
max-temps in affected programs: 4191 -> 3777 (-9.88%)
helped: 113
HURT: 22
Max-temps are helped.

total sfu-stalls in shared programs: 31584 -> 31616 (0.10%)
sfu-stalls in affected programs: 217 -> 249 (14.75%)
helped: 51
HURT: 54
Inconclusive result (value mean confidence interval includes 0).

total inst-and-stalls in shared programs: 13763247 -> 13753165 (-0.07%)
inst-and-stalls in affected programs: 98719 -> 88637 (-10.21%)
helped: 187
HURT: 134
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9681>
 2021-03-22 12:17:13 +00:00
Iago Toral Quiroga
1c987f5db3 broadcom/compiler: optimize constant vfpack 
total instructions in shared programs: 13733627 -> 13731663 (-0.01%)
instructions in affected programs: 174140 -> 172176 (-1.13%)
helped: 1597
HURT: 310
Instructions are helped.

total uniforms in shared programs: 3784601 -> 3780693 (-0.10%)
uniforms in affected programs: 58678 -> 54770 (-6.66%)
helped: 2886
HURT: 3
Uniforms are helped.

total max-temps in shared programs: 2322714 -> 2319942 (-0.12%)
max-temps in affected programs: 15729 -> 12957 (-17.62%)
helped: 2189
HURT: 1
Max-temps are helped.

total spills in shared programs: 6010 -> 6012 (0.03%)
spills in affected programs: 61 -> 63 (3.28%)
helped: 0
HURT: 1

total fills in shared programs: 13494 -> 13497 (0.02%)
fills in affected programs: 89 -> 92 (3.37%)
helped: 0
HURT: 1

total sfu-stalls in shared programs: 31521 -> 31584 (0.20%)
sfu-stalls in affected programs: 328 -> 391 (19.21%)
helped: 30
HURT: 94
Inconclusive result (%-change mean confidence interval includes 0).

total inst-and-stalls in shared programs: 13765148 -> 13763247 (-0.01%)
inst-and-stalls in affected programs: 174237 -> 172336 (-1.09%)
helped: 1551
HURT: 316
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9681>
 2021-03-22 12:17:13 +00:00
Iago Toral Quiroga
b189409a46 broadcom/compiler: handle implicit uniform loads when optimizing constant alu 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9681>
 2021-03-22 12:17:13 +00:00
Samuel Pitoiset
92764abc82 radv: add RADV_DEBUG=novrsflatshading option 
To easily debug if enabling VRS for flat shading is broken.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>
 2021-03-22 12:36:26 +01:00
Samuel Pitoiset
f5540209ab radv: enable VRS 2x2 coarse shading for flat shading on GFX10.3+ 
This should safe to enable and shouldn't degrade the quality.
It decreases the number of PS invocations by 4 when used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>
 2021-03-22 12:36:26 +01:00
Samuel Pitoiset
cf54ff3ea6 radv: determine if a pipeline is candidate for flat shading 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>
 2021-03-22 12:36:25 +01:00
Samuel Pitoiset
abc64caef9 radv: gather if the FS uses perspective or linear interpolations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>
 2021-03-22 12:35:35 +01:00
Samuel Pitoiset
b2c1ed262d radv: restore previous MRT CB_SHADER_MASK logic 
It was moved to the shader info pass to compute MRTs from the shader
outputs to fix some CTS failures but this is actually unnecessary.
The CTS failures were actually CTS bugs.

This reverts 70cc80805c ("radv: compute CB_SHADER_MASK from the
fragment shader outputs") and 76ee45d3a8 ("radv: adjust CB_SHADER_MASK
for dual-source blending in the shader info pass").

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9703>
 2021-03-22 11:32:49 +00:00
Tony Wasserka
2fb71504f0 radv: Skip 0-sized index buffers only when necessary 
This workaround is only needed on Navi10 and Navi14.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>
 2021-03-22 11:47:25 +01:00
Tony Wasserka
ec34a9a889 ac: Add has_zero_index_buffer_bug to ac_gpu_info 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>
 2021-03-22 11:47:22 +01:00
Tony Wasserka
dad3cda66c radv: Fix improper max_index_count argument for indexed draws 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3598
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>
 2021-03-22 11:46:59 +01:00
Samuel Pitoiset
35816188b7 radv: initialize CMASK with correct clear codes 
From AMDVLK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9650>
 2021-03-22 10:23:05 +01:00
Samuel Pitoiset
fdc0009962 radv: fix clearing CMASK layers on GFX9+ 
The driver was clearing all layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9650>
 2021-03-22 10:23:03 +01:00
Samuel Pitoiset
74a3f48987 ac/surface: init CMASK slice size on GFX9+ 
It was only set for GFX6-8.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9650>
 2021-03-22 10:23:00 +01:00
Marcin Ślusarz
b0452f150e intel/aub_viewer: fix decoding of sampler states 
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
186301a232 intel/aub_viewer: drop bogus check 
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
2b5f9602b7 intel/aub_viewer: catch invalid sampler state pointer 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
08f8677b29 intel/batch_decoder: assert on invalid sampler pointer 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
56cd91bc7c intel/batch_decoder: fix decoding of sampler states 
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
cd0f9cdb6e intel/batch_decoder: drop bogus check 
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
bb8ee5f52d intel/batch_decoder: catch invalid sampler state pointer 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
31178db610 i965: fix decode_get_bo 
Similar fix to the iris one.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz
f33852e268 iris: fix decode_get_bo 
It tries to be helpful by returning BO metadata matching exactly
the requested address, but it "forgets" to fix the remaining size.
The only caller of this function (ctx_get_bo) already deals with
raw BO metadata, so return it as such instead of fixing size too.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Vasily Khoruzhick
5762aa4e56 lima: relax checks of imported BO 
We don't need stride of imported buffer to be equal to calculated
stride if the buffer is linear.

Fixes #3070

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9646>
 2021-03-22 04:23:23 +00:00
Dave Airlie
b06f121fcc lavapipe: enable 8/16-bit storage extensions 
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
 2021-03-22 12:17:36 +10:00
Dave Airlie
27822a6f0b gallivm: use fp16 casts lowering 
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
 2021-03-22 12:17:31 +10:00
Dave Airlie
48080e5bdf nir: lower 64-bit floats to 32-bit first. 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
 2021-03-22 12:17:14 +10:00
Dave Airlie
01dfd65a2d nir: port fp16 casting code from dxil 
This moves the dxil pass to common code and makes dxil
use the new code.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
 2021-03-22 12:16:59 +10:00
Dave Airlie
224069cefd gallivm/nir: handle bool registers. 
lowering to 32-bit bools doesn't get rid of register stores,
so handle those.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
 2021-03-22 12:16:45 +10:00
Dave Airlie
2a9e98130b gallivm: fix non-32bit ubo loads 
8/16-bit storage requires ubo loads for the smaller types,
fix the ubo loading and bounds checking.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>
 2021-03-22 12:16:14 +10:00
Arno Messiaen
07080fd4c9 lima/ppir: increase usage of pipeline regs 
It's possible to increase usage of ppir_pipeline_reg_fmul and
ppir_pipeline_reg_vmul by reordering arguments in some cases, so let's
do that.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3232>
 2021-03-22 01:31:11 +00:00
Jesse Natalie
55d153b9f5 nir: Temporarily disable optimizations for MSVC ARM64 
There's currently an MSVC optimizer bug which causes a stack overflow
in the compiler if it attempts to optimize fsat.

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9700>
 2021-03-21 21:41:41 +00:00
Ilia Mirkin
3e68e7f90d gallium,st: add missing viewport swizzles 
Viewports must be initialized with the appropriate swizzles (for
hardware that supports this feature).

Fixes: 90fcb3fef2 (st/mesa: add NV_viewport_swizzle support)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9732>
 2021-03-21 18:29:50 +00:00
Rob Clark
befd9fbbba freedreno/a6xx: Fix typo 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>
 2021-03-21 16:01:01 +00:00
Rob Clark
5b96689fa0 freedreno: Autotune bypass vs GMEM rendering decision 
In some cases, like gl_driver2, we have all the characteristics that
make our current simplistic bypass vs GMEM decision pick GMEM (ie. batch
starts with a clear, has blend enabled, has a high draw count, etc),
but each draw touches very few pixels and the per-tile state-change
overhead leaves us CP limited.  We would be better in this case picking
the bypass path.

So use feedback from # of samples-passed in previous render passes to
the same FBO to give us a bit more information to make better choices.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2798
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>
 2021-03-21 16:01:01 +00:00
Rob Clark
0610c7ba84 freedreno/a6xx: Fix sRGB/snorm vs sysmem clear path 
This shows up when, thanks to the next patch, we decide to start doing
bypass instead of GMEM for some dEQP's

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>
 2021-03-21 16:01:01 +00:00
Rob Clark
2e529ed7ef freedreno: Add gmem_reason_mask 
Older gens had more restrictions about GMEM bypass which do not apply to
newer generations.  Add a bitmask so we know which bits are not a hard
requirement for using GMEM.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>
 2021-03-21 16:01:01 +00:00