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Author SHA1 Message Date
Alyssa Rosenzweig
957f326a10 brw: drop printf info plumbing 
unused since printf hashing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:10 +00:00
Alyssa Rosenzweig
58fd54b56e anv,hasvk: do not use unify_interfaces 
it's GLSL cruft we want to get rid of.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:10 +00:00
Alyssa Rosenzweig
bbf5bc8632 brw: cleanup int64 option set 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:09 +00:00
Alyssa Rosenzweig
168704c2fe brw: hoist shared options out of the stage loop 
ideally we'd have no stage switching, but this is just a cleanup for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:09 +00:00
Alyssa Rosenzweig
0d7083d5bc brw: drop indirection on compiler options 
I see no point, we allocate for every shader stage anyway. This is a bit
simpler.

I'm not a fan of the brw_compiler singleton at all but torching that is not on
today's agenda. Flattening it a little bit very much is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:08 +00:00
Alyssa Rosenzweig
2c161cc35d brw: drop unused brw_kernel code 
unused since we dropped GRL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:07 +00:00
Alyssa Rosenzweig
c0c70cb392 nir/lower_flatshade: clean up 
while in the area.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37448>
 2025-09-18 13:37:03 +00:00
Rhys Perry
d6ed68212c aco: fix SGPR 8-bit nir_op_vec with mixed constant and non-constant 
For example, vec2(non_const, const)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04e3d7ad93 ("aco: improve nir_op_vec with constant operands")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13911
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37405>
 2025-09-18 12:37:19 +00:00
Mary Guillemard
27f9e706f8 panvk: Properly set shader binary properties 
We do not support VK_EXT_shader_object so far but vk_shader layer
depends on those values so we should fill them.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Mary Guillemard
e4fea2bc46 panvk: Follow nir_lower_io for subpass lowering 
We now set fb_fetch_output and fb_fetch_output_coherent to be consistent
with nir_lower_io.

This has no impact in general unless some generic pass depends on those
infos.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Mary Guillemard
d9b11cd7a2 nir/print: Fix load_converted_output_pan and load_readonly_output_pan 
We were not printing IO infos properly for those intrinsics.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Christian Gmeiner
2d8f8f82bd etnaviv: blt: Enable scissored clear 
The main challenge is handling tile status (TS) correctly. Full clears
simply mark tiles as "cleared" in TS metadata without touching pixels.
Scissored clears must first decompress existing TS tiles using the
current clear color, then apply the new color to the scissor region.

The implementation maintains the original surface clear color for TS
decompression operations while using the new color for actual clearing.
This prevents rendering artifacts when mixing BLT and 3D operations.

BLT engine operates directly with pixel positions and handles all TS
tile complexity automatically.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35956>
 2025-09-18 10:24:19 +00:00
Eric Engestrom
f2c4c5493e radv: add comment explaining why fp16 is disabled by default on gfx8 
Suggested-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
 2025-09-18 09:08:21 +00:00
Eric Engestrom
1ee1e63bdb radv: make sure fp16 is enabled consistently on gfx8 
Fixes `dEQP-VK.api.info.vulkan1p4_limits_validation.general`

Fixes: f0f4ae1713 ("radv: Add radv_enable_float16_gfx8 drirc and enable for Indiana Jones TGC")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
 2025-09-18 09:08:21 +00:00
Qiang Yu
faebbf9640 mesa: fix draw mesh shader indirect buffer size check 
We should not count the last draw command stride padding in
the indirect buffer.

Fixes: 176740c26f4 ("mesa: implement mesh shader draw calls")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37392>
 2025-09-18 01:38:08 +00:00
Chia-I Wu
85ec0fffa2 panvk: use common calibrated timestamp support 
It does not look like our custom version has anything special to offer.

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37421>
 2025-09-17 22:55:23 +00:00
Chia-I Wu
e9444b28fd panvk: require gpu_can_query_timestamp for calibrated timestamps 
Advertise the extensions without VK_TIME_DOMAIN_DEVICE_KHR support is
not very useful.

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37421>
 2025-09-17 22:55:23 +00:00
Paulo Zanoni
25d26a89e3 isl: allow sparse with STC_CCS on DG2 
Thanks to Nanley Chery for pointing out this possibility.

v2: Make it simpler (Nanley).

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37419>
 2025-09-17 21:42:58 +00:00
Paulo Zanoni
7dd66d6bb1 isl: allow sparse with CCS on Xe2 and newer 
When the auxiliary surface is handled by the hardware directly,
there's nothing to bind besides the main pixels, so we can allow
sparse without doing anything else. We can't do this in the exact same
way with DG2 (which has_flat_ccs) because it uses the
aux_state_tracking_buffer.

v2: Fix spelling (Nanley).

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37419>
 2025-09-17 21:42:58 +00:00
Paulo Zanoni
e7fd99c205 intel: rework the way sparse forces CCS/MCS/HIZ to be disabled 
We want to be a little more granular than just "aux surfaces are
completely incompatible with sparse!", so have each of
isl_surf_get_*_surf disable itself when sparse is used.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37419>
 2025-09-17 21:42:58 +00:00
Gert Wollny
3b3c3ccf56 nir+r600: add option to avoid contracting fabs into ffma 
On r600 ternary operations can't use the fabs source modifier, so
converting "fadd(fabs(fmul(a, b), c)" to  "ffma(fabs(a), fabs(b), c)"
adds one more instruction in the backend, hence avoid this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37440>
 2025-09-17 21:03:58 +00:00
Christian Gmeiner
a7d2570296 nir/opt_algebraic: optimize f2i32(fround_even(x)) to f2i32_rtne(x) 
Add late optimization to fuse f2i32 and fround_even operations into a
single f2i32_rtne instruction when the intermediate fround_even result
is only used once. This eliminates redundant rounding since f2i32_rtne
performs round-to-nearest-even conversion directly.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37426>
 2025-09-17 20:31:59 +00:00
Emma Anholt
0f320b7a1d d3d10umd: Add missing dependency on u_formats codegen. 
Fixes this error during Shader.cpp build:

..\src\util/format/u_formats.h(33): fatal error C1083: Cannot open include file: 'util/format/u_format_gen.h': No such file or directory

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:04:37 -07:00
Emma Anholt
114e6a3104 ir3: Use a linear allocation context for ir3_instructions. 
Again, instrs don't get freed as we go, so the linear gc context saves us
5 pointers per instr.

Fossil replay time for deadspace3 on a debugoptimized build -4.85258% +/-
3.04009% (n=10)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:02:47 -07:00
Emma Anholt
12fae29ec2 ir3: Use a linear allocation context for ir3_registers. 
Since we don't free registers as we go, we can just allocate them in a
linear gc context that gets freed at ralloc destroy.  Saves 5 pointers of
memory per register for the ralloc overhead.

Fossil replay time for deadspace3 on a debugoptimized build -4.30353% +/-
1.80078% (n=10).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:02:47 -07:00
Emma Anholt
1b4c2c1566 ir3: Use a bitset for the defs-seen table. 
Fossil reply time for deadspace3 on a debugoptimized build -3.20856% +/-
1.48994% (n=15).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:02:47 -07:00
Eric Engestrom
144879ca40 doc/features.txt: add missing supported dzn extensions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37404>
 2025-09-17 16:09:29 +00:00
Eric Engestrom
102017f2ca docs: add sha sum for 25.2.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37446>
 2025-09-17 16:04:42 +00:00
Eric Engestrom
d816a0eb2a docs: add release notes for 25.2.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37446>
 2025-09-17 16:04:42 +00:00
Eric Engestrom
b0171edda7 docs: update calendar for 25.2.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37446>
 2025-09-17 16:04:42 +00:00
Icenowy Zheng
44aa7cfb4f pvr: implement samplerAnisotropy 
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36242>
 2025-09-17 15:44:32 +00:00
Dylan Baker
209deff350 calendar: Update release dates and change 25.3 to Dylan 
We'll pull the calendar in to regularly scheduled time, and then cut a
couple of 25.2 releases we shouldn't need.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37443>
 2025-09-17 15:39:14 +00:00
Karmjit Mahil
9c6183604f nir, ir3: Add lower_fmulz_with_abs_min backend option 
This commits adds the `lower_fmulz_with_abs_min` which lowers
`fmulz` -> `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`
`ffmaz` -> `min(abs(a), abs(b)) == 0.0 ? c : ffma(a, b, c)

This is useful for ISAs which have `abs` for free on `min` such as
ir3.

Adreno A750 Benchmark of 10 runs of 5 DX9 single frame trimmed
captures looped 2048 times using u_trace measuring
`start_render_pass` to `end_render_pass` results:

sysmem:
-1.91156%, -2.21791%, -2.02533%, -2.21666%, -2.33272%,
-2.67349%, -1.75278%, -2.05923%, -2.26892%, -2.10506%
Avg:  ~ -2.16%
ST.S: ~  0.25%

gmem:
-3.61496%, -3.66682%, -3.80901%, -3.51198%, -3.72950%,
-3.71413%, -3.64467%, -3.67092%, -3.90640%, -3.83888%
Avg:  ~ -3.71%
ST.S: ~  0.12%

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
 2025-09-17 15:02:50 +00:00
Karmjit Mahil
8d19ffef0a nir: Add more matches for fmulz 
In some cases after other passes, `(a == 0.0 ? 0 : b)` can be
turned into `(a != 0.0 ? b : 0)`, so let's match those cases too.

Also matching `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
 2025-09-17 15:02:50 +00:00
Mike Blumenkrantz
c85168160e zink: reset batch states on destroy 
these may otherwise have been in the reset queue and thus contain
resource refs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:26 -04:00
Mike Blumenkrantz
2330839641 zink: null out zink_batch_state::ctx when adding to the screen list 
this otherwise leaves a dangling pointer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:25 -04:00
Mike Blumenkrantz
e64f0414b3 zink: check for zink_batch_state::ctx before using during descriptor state reset 
this is a screen function, so ctx may be null

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:23 -04:00
Mike Blumenkrantz
0df1fcd0b3 zink: call post_submit directly from submit_queue 
this should all happen as a unit to ensure the batch state is not
modified before post_submit mechanics trigger

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:21 -04:00
Mike Blumenkrantz
7e101873ea zink: prune active queries in reset_batch_state_ctx() 
these need the context

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:19 -04:00
Mike Blumenkrantz
6369dbd6be zink: account for kopper dt not having a swapchain when pruning batch usage 
this could be pending deletion

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:18 -04:00
Mike Blumenkrantz
61633e0a2e zink: wait on queues during screen destroy 
there might somehow be operations active

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36289>
 2025-09-17 11:59:19 +00:00
Rhys Perry
8931672eef aco: workaround load tearing for load_shared2_amd 
This probably has the same issue as load_shared.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04956d54ce ("aco: force uniform result for LDS load with uniform address if it can be non uniform")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry
810d4ff299 nir/lower_atomics: set ACCESS_COHERENT 
The lack of ACCESS_COHERENT was probably fine, the worst it would do would
add a pointless iteration after loading an out-of-date value.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry
e819160705 nir/lower_atomics_to_ssbo: set ACCESS_COHERENT for loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry
a0a458c445 zink/ntv: use MakePointerAvailable/Visible for shared load/store 
These are always workgroup coherent in NIR.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry
5d2c17a5fd vtn: skip make-available/visible for shared 
These barriers could prevent optimizations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry
d1e230454d zink/ntv: fix coherent image load/store 
The SPIR-V didn't seem to use coherent load/store.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Eric Engestrom
f99230cc67 docs/release-calendar: add 25.2.x dates, and 25.3 branchpoint and release candidates 
I'm having hip surgery (same surgery as last year, other hip) on Oct 22,
which I'm hoping goes well and hoping (and expecting) that I'll have
recovered enough after a week to be able to sit with my laptop for long
enough chunks to do release management.

Worst case, if I can't do it I'll push back the 25.2.6 release by
a week, but I think I'll keep the branchpoint as that one doesn't take
much work as there's nothing to backport, just creating a couple of
branches and tags, and setting up a worktree locally which I can do in
advance (and have just done so).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37435>
 2025-09-17 11:11:34 +00:00
Christoph Pillmayer
cc5c1c65ef pan/va: Remove redundant MOVs from va_lower_split_64bit 
To lower 64bit sources we emit a COLLECT -> SPLIT pair to force
allocation into consecutive registers. When the sources for COLLECT
are outputs of the same SPLIT already, we can omit the COLLECT + SPLIT
pair.

Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37398>
 2025-09-17 10:44:14 +00:00
Jose Maria Casanova Crespo
c83fddb9ed v3d: use helpers util_writes_depth/stencil 
The helpers already take into account when depth/stencil ops
don't imply writes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37397>
 2025-09-17 10:27:31 +00:00