4af079960d
intel/compiler: Enable lower_rotate_to_shuffle in subgroup lowering
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27272 >
2024-01-25 19:07:42 +00:00
2e38024fd8
intel: Use hardware generated compute shader local invocation IDs
...
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27167 >
2024-01-25 08:43:04 +00:00
5e7f4ff97f
intel: Add driver support for hardware generated local invocation IDs
...
This adds a few new fields in the brw_cs_prog_data struct and then
uses them to fill in the relevant COMPUTE_WALKER fields.
Although the Tile Layout field theoretically has different settings for
32/64/128bpe, it appears that the recommended programming is to always
pick either TileY 32bpe or Linear. It's not very practical to look at
the surface formats involved, anyway.
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27167 >
2024-01-25 08:43:04 +00:00
10ed4f1cab
intel/nir: Pass devinfo and prog_data to brw_nir_lower_cs_intrinsics
...
We'll want to check for Alchemist and set various prog_data fields
in the next patch, in order to enable some optimizations. Passing
NULL for prog_data will remain valid and continue working as before.
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27167 >
2024-01-25 08:43:04 +00:00
c2a25cf75c
intel/fs: Fix shift counts for 8- and 16-bit types
...
With regards to implicit masking of the shift counts for 8- and 16-bit
types, the PRMs are incorrect. They falsely state that on Gen9+ only the
low bits of src1 matching the size of src0 (e.g., 4-bits for W or UW
src0) are used. The Bspec (backed by data from experimentation) state
that 0x3f is used for Q and UQ types, and 0x1f is used for **all** other
types.
To match the behavior expected for the NIR opcodes, explicit masks for
8- and 16-bit types must be added.
This fixes (the updated version, see crucible!138) of
func.shader.shift.int16_t on all Intel platforms. According to Karol,
this also fixes "integer_ops integer_rotate" tests in OpenCL CTS.
No shader-db or fossil-db changes on any Intel platform.
Tested-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23001 >
2024-01-24 19:41:35 +00:00
6fcec87090
intel/fs: Track instance id in gs_thread_payload
...
This change moves the instance id gs_thread_payload constructor and
lowering code will simply use that.
Also, this change takes the Xe2 register width in consideration that
fixes a couple of tests involving geometry shaders with gl_InvocationID
on Xe2.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26960 >
2024-01-22 22:15:38 +00:00
f2b7c4ce29
nir: rework and fix rotate lowering
...
No driver supports urol/uror on all bit sizes. Intel gen11+ only for 16
and 32 bit, Nvidia GV100+ only for 32 bit. Etnaviv can support it on 8,
16 and 32 bit.
Also turn the `lower` into a `has` option as only two drivers actually
support `uror` and `urol` at this momemt.
Fixes crashes with CL integer_rotate on iris and nouveau since we emit
urol for `rotate`.
v2: always lower 64 bit
Fixes: fe0965afa6kherbst@redhat.com >
Reviewed-by (Intel and nir): Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com >
Acked-by: Yonggang Luo <luoyonggang@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27090 >
2024-01-22 10:27:44 +00:00
c3a64f8dd1
intel/fs/xe2+: Allow SIMD16 MULH instructions.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165 >
2024-01-20 19:55:31 +00:00
54f3d5a00c
intel/fs: Emit QUAD_SWIZZLE instructions with WE_all for derivative lowering.
...
Otherwise the code generator will attempt to emit SIMD-lowered
QUAD_SWIZZLE instructions with an execution group not multiple of 8,
which is invalid on Xe2+.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165 >
2024-01-20 19:55:31 +00:00
3e710a84ad
intel/fs: Set the default execution group to 0 when not representable by the platform.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165 >
2024-01-20 19:55:31 +00:00
43c9620dbf
intel/eu/xe2+: Translate brw_reg fields in REG_SIZE units to physical 512b GRF units during codegen.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165 >
2024-01-20 19:55:31 +00:00
8bc3821520
intel/fs/xe2+: Disable bank conflict mitigation pass for now.
...
Reworks:
* Added a TODO comment.
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165 >
2024-01-20 19:55:31 +00:00
6efcba9e36
intel/ir/xe2+: Add support for 32 SBID tokens to performance model.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165 >
2024-01-20 19:55:31 +00:00
4dbf9181cd
intel/compiler: Fix rebuilding the CFG in fs_combine_constants
...
When building the CFG the instructions are taken of the list in
fs_visitor and added to the lists inside each block. The single
"exec_node" in the instruction is used for those memberships.
In the case the pass rebuilt the CFG, it had no instructions, so
calculate_cfg() had nothing to work with. For now fix the bug by
pulling all the instructions back to the original list.
We can do better here, but punting until upcoming work on
CFG itself.
Issue found in an unpublished CTS test. Small reproduction in our
unit tests now enabled.
Fixes: 65237f8bbcian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27131 >
2024-01-19 01:59:36 +00:00
e9bfdcf576
intel/compiler: Add couple of tests for fs_combine_constants
...
Add a simple test to kick off the infrastructure. And also a test
(for now disabled) that fails because the code is returning an
empty shader. Next patch will fix and enable it.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27131 >
2024-01-19 01:59:36 +00:00
7481d61a5d
intel/compiler: Track mue_compaction and mue_header_packing flags in brw_get_compiler_config_value
...
v2: Use u_foreach_bit64. Suggested by Lionel.
Fixes: 48885c7fe3lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993 >
2024-01-18 19:20:12 +00:00
6f237a23c7
intel/compiler: Track lower_dpas flag in brw_get_compiler_config_value
...
This user-settable flag affects compiler output, so it should be tracked
in the cache hash.
Fixes: 3756f60558lionel.g.landwerlin@intel.com >
Suggested-by: Lionel Landwerlin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993 >
2024-01-18 19:20:12 +00:00
2741c6464c
intel/compiler: Use u_foreach_bit64 in brw_get_compiler_config_value
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Suggested-by: Lionel Landwerlin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993 >
2024-01-18 19:20:12 +00:00
951e08fc18
intel/compiler: Disable DPAS instructions on MTL
...
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 3756f60558Closes : #10376
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26993 >
2024-01-18 19:20:12 +00:00
73835874a8
intel/disasm: Remove duplicate variable reg_file
...
Fix defects reported by Coverity Scan.
Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In reg_file = reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst),
reg_file is written twice with the same value.
Fixes: 1c92dad5cbvlee@freedesktop.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27056 >
2024-01-15 07:46:12 +00:00
1a31970946
intel/compiler/xe2: Implement instruction compaction for DPAS.
...
These use different tables but map to the same bits, so it is just
a matter of picking the right tables for the instruction.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
6e56a4b474
intel/compiler/xe2: Fix for the removal of AccWrCtrl.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
7f39e51dd5
intel/compiler/xe2: Add extra flag registers.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
f974eacab3
intel/compiler/xe2: Fix for the removal of most predication modes.
...
Reworks:
* Remove changes to fixup_nomask workaround since it applies only for
Gfx12 family.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
f79123e1d9
intel/compiler/xe2: Fix for NibCtrl field removal.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
7db3f0b1c1
intel/compiler/xe2: Implement instruction compaction.
...
Reworks:
* Handle DPAS in has_3src_unmapped_bits.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
57ba9c176c
intel/compiler/xe2: Implement codegen of compact instructions.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
d8ba1d63bc
intel/compiler: Add assume() checks to brw_compact_inst_(set_)bits().
...
Similar to the preconditions of brw_inst_(set_)bits().
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
4a24f49b57
intel/compiler/xe2: Implement codegen of three-source instructions.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
e10e7d5aa3
intel/compiler/xe2: Implement codegen of indirect immediates.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
294bdbb253
intel/compiler/xe2: Implement codegen of 2-source instruction operands.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
72bbfa8e8d
intel/compiler/xe2: Implement codegen of general instruction controls.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
066e6c6234
intel/compiler/xe2: Add Xe2 bounds to FF() macro.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26860 >
2024-01-12 20:18:03 +00:00
ae29ffb637
intel/eu/gfx12.5+: Don't fail validation with ARF register restriction error for indirect addressing.
...
The "file" field doesn't exist for indirect operands, so it contains
garbage.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26994 >
2024-01-12 00:20:38 +00:00
32b3ea3c3d
intel/eu/validate: SEND instructions don't have immediate encodings on Gen12+.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26994 >
2024-01-12 00:20:38 +00:00
dfb034853a
intel/fs: Use full 32-bit sample masks when immediate.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26994 >
2024-01-12 00:20:38 +00:00
98665e024f
intel/tools/i965_asm: Handle sync instruction
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
cfb34dc695
intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
dbf6f0291a
intel/fs: Set group 0 for Wa_14010017096 MOV instruction
...
We always set exec size to 16 for this MOV, but the execution group remains
from the previous emitted instruction. This can cause emitting a group
which violates PRM restriction for ChanOff: "The execution size (ExecSize)
must be a factor of the chosen offset."
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
173a991405
intel/disasm: Print src1_len correctly depending on ExDesc type
...
There are two "Src1.Length" with different formats in "send" description
in the PRMs. One is part of ExMsgDesc, is relevant for LSC SFIDs, and
exists if [ExDesc.IsReg]==false. The other is just a 5-bit immediate,
is relevant for other SFIDs too, and exists if ([ExDesc.IsReg]==true)
AND ([ExBSO]==true).
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
b5c0b90402
intel/compiler: Set flag reg to 0 when disabling predication
...
Having the reg set with predication disabled shouldn't cause any problems
during the execution. But when decompiling such instruction the flag won't
be shown in the output, so the recompiling will cause
functionally-identical but binary-different code. Fixing this makes
disasm/asm testing easier.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
a129e136de
intel/disasm: Print half-float values instead of placeholder
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
4f41c44df2
intel/compiler: Add variable to dump binaries of all compiled shaders
...
This can be useful for testing i965_disasm and i965_asm by comparing
bin -> asm -> bin results.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:51 +00:00
ef88a20d96
intel/compiler: Use INTEL_DEBUG=cs to ask for brw_compiler output
...
This removes output like
```
CS SIMD16 shader: 2790 inst, 0 loops, 24804 cycles, 166:106 spills:fills, 35 sends,
scheduled with mode top-down, Promoted 1 constants, compacted 44640 to 41424 bytes.
```
from the default builds. Like other debug output in intel_clc, they can
re-enabled with INTEL_DEBUG=cs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939 >
2024-01-09 01:26:41 +00:00
4b30b46ffd
intel/fs: fix depth compute state for unchanged depth layout
...
There is no VK CTS exercising this case. If there was we would run
into hangs as noticed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26923 >
2024-01-08 17:28:12 +00:00
77f4f3112d
intel/fs: Use linear allocator in fs_live_variables
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670 >
2024-01-04 23:06:07 +00:00
b5cd91501d
intel/fs: Use linear allocator in opt_copy_propagation
...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670 >
2024-01-04 23:06:07 +00:00
6d2503e935
intel/fs: Only allocate acp_entry if we are adding one
...
In practice it seems we are always entering here, haven't looked
in detail whether at this point we could just assert. But for now
only allocate a new acp_entry if we are going to add it.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25670 >
2024-01-04 23:06:07 +00:00
96e0d979a7
intel/fs: Check fs_visitor instance before using it
...
On Xe2+, we don't build the SIMD8 shader so this check makes sure we
don't execute the uninitialized invocations.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26886 >
2024-01-04 22:24:07 +00:00
56a72e014f
intel/compiler: reemit boolean resolve for inverted if on gen5
...
Gen5 adds some boolean conversion instructions after nir emits,
but that nir srcs don't line up with them, so reemit the boolean
conversion if we reemit the inot.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 31b5f5a51fhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26782 >
2024-01-04 21:27:23 +00:00
Caio Oliveira