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7540 Commits

Author SHA1 Message Date
Andres Gomez 07b86e64a5 ci: add VKD3D-Proton testsuite job for radv's Navy Flounder 
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
 2021-05-25 17:03:25 +00:00
Andres Gomez 537c9460fa ci: add radv's trace job for Navy Flounder 
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
 2021-05-25 17:03:25 +00:00
Andres Gomez a71ffa4592 ci: uprev DXVK to 1.8.1 
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
 2021-05-25 17:03:25 +00:00
Andres Gomez fa8ca10e27 ci: remove radv's trace job for Polaris10 
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
 2021-05-25 17:03:25 +00:00
Andres Gomez f0f812dbe7 ci: update radv's trace job tag for Raven 
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10870>
 2021-05-25 17:03:25 +00:00
Marek Olšák 13acbaecd8 radeonsi: rewrite the prefix sum computation for shader culling 
Instead of storing the vertex mask per wave into LDS and then computing
the prefix sum, store 8-bit bitcounts (vertex counts) of the vertex masks
into LDS. This allows us to compute the sum using v_sad_u8, which computes
a sum of 4 i8vec4 components in one instruction.

Each i8vec4 of vertex counts is loaded in parallel threads (one dword
per thread) instead of all being loaded in thread 0, and readlane copies
them to SGPRs instead of readfirstlane.

LDS is no longer initialized before culling. Instead, the counts for
inactive waves are masked with AND later.

Incorrect old comments are also fixed.

This change removes 80 bytes from the code size, and it allows increasing
the workgroup size from 128 to 256. (which is the main motivation for this)

Now changing the workgroup size with wave64 has no effect on the code size.
Switching to wave32 with 8 waves even generates slightly smaller code than
wave64 with 4 waves.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 4602147561 ac/llvm: don't draw the primitive for the dummy export workaround for Navi1x 
for conservative rasterization

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák f33500b187 ac/llvm: set range metadata on mbcnt and deduplicate get_thread_id 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 57e182c75b ac/llvm: allow ac_build_optimization_barrier with SGPRs, pointers, and metadata 
sgpr=true prevents moving the value to a VGPR.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 5f33f80dc7 ac/llvm: expose set_range_metadata to more users 
I sometimes use it for experiments. It will be used later.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 94a1f45e15 ac/llvm: set target features per function instead of per target machine 
This is a cleanup that allows the removal of the wave32 target machine and
the wave32 pass manager.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 38d3c4251d ac/gpu_info: set has_zero_index_buffer_bug for Navi12 too 
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák fbecc47430 amd: fix incorrect addrlib comment for HTILE equations 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák ade5d9c2a7 amd/registers: regenerate json files without 32-bit register fields 
Only a few of those were used in drivers.

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 72362f2830 amd/registers: don't generate 32-bit register fields 
This removes confusing register types due to deduplication, such as:
   "name": "SQ_WAVE_TTMP10",
   "type_ref": "SPI_SHADER_USER_DATA_PS_0"

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:43 +00:00
Samuel Pitoiset 287c06228c radv: remove an useless TODO for dynamic line width 
We can't do anything it seems.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10881>
 2021-05-25 14:11:44 +00:00
Samuel Pitoiset eaef5c2934 radv: ignore dynamic blend constants if blend isn't enabled 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10881>
 2021-05-25 14:11:44 +00:00
Timur Kristóf c783293e47 aco: Don't eliminate exec write when it's used by a copy later. 
Fixes: bc13049747
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10920>
 2021-05-25 13:50:43 +00:00
Yiwei Zhang c8e90a022e radv: fix AHB leak upon exportable allocation 
A successful AHardwareBuffer_allocate itself will increase a refcount on
the newly allocated AHB. For the import case, the implementation must
acquire a reference on the AHB. So if we layer the exportable allocation
on top of AHB allocation and AHB import, we must release an AHB
reference to avoid leak.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10940>
 2021-05-25 06:31:25 +00:00
Marek Olšák 80f0726e4c amd: add Beige Goby support 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
 2021-05-24 17:41:34 +00:00
Aaron Liu c54bb135aa amd: add Yellow Carp support 
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
 2021-05-24 17:41:34 +00:00
Samuel Pitoiset a00be79d80 radv: remove small overhead of radv_pipeline_has_ngg() 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4784
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10908>
 2021-05-24 08:50:47 +00:00
Samuel Pitoiset ca783612e7 radv: simplify radv_pipeline_has_gs_copy_shader() 
The GS copy shader should only be built if GS and without NGG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10908>
 2021-05-24 08:50:47 +00:00
Samuel Pitoiset e98c61e9f3 radv: fix fast clearing DCC if one level can't be compressed on GFX10+ 
Fallback to a slow clear, this could be improved by splitting the
clear into two parts (one fast and one slow) but that's complicated.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10516>
 2021-05-24 08:28:48 +00:00
Tomeu Vizoso 36e6367747 radv/ci: Test on Stoney on CI 
Run part of the VK CTS in 3 devices with Stoney Ridge graphics.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10853>
 2021-05-24 07:44:00 +02:00
Yogesh Mohanmarimuthu cd34c7f5b8 radv: set RADEON_FLAG_GTT_WC flag for prime memory 
With display on iGPU and render on dGPU, VRR is not working. To fix
this set RADEON_FLAG_GTT_WC flag when allocating memory for prime. This
allows kernel function amdgpu_display_user_framebuffer_create() to
allocate GTT memory with USWC flag making the buffer scanout for iGPU.
This helps the ddx amdgpu_present_check_flip() function to return
true. Now, xserver will flip the framebuffer instead of blit. Due
to this VRR feature will work where iGPU supports USWC flag.

v2: modify commit message with use case (Michel Dänzer)
v3: allow GTT_WC flag only if VRAM_DOMAIN and NO_CPU_ACCESS (Bas Nieuwenhuizen)
v4: add check for wsi_info is NULL
v5: use wsi_info pointer to check for prime alloc (Bas Nieuwenhuizen)
v6: set _GTT_WC flag when wsi_info pointer is not NULL (Bas Nieuwenhuizen)

Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10657>
 2021-05-23 11:00:17 +05:30
Andres Gomez b663c54417 ci: update some radv trace checksums 
After a7c0cf500b ("radv: Enable DCC for image stores on GFX10.")
some checksums for the radv driver remained to be updated.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>
 2021-05-22 06:26:28 +00:00
Andres Gomez 4b12771f8d ci: update some radv trace checksums 
After 524848707b ("radv: don't set sx_blend_opt_epsilon for V_028C70_COLOR_10_11_11")
some checksums for the radv driver remained to be updated.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>
 2021-05-22 06:26:28 +00:00
Samuel Pitoiset 726cb2d6f6 ac: ac_gpu_info::has_vgt_flush_ngg_legacy_bug 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10911>
 2021-05-21 19:46:56 +00:00
Daniel Schürmann 32c7d17120 aco: remove condition operand from branch in invert block 
As value numbering only handles logical blocks, this
could lead to invalid IR until insert_exec_mask().
No fossil-db changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10894>
 2021-05-20 17:44:20 +00:00
Timur Kristóf 2bb1bf78f0 radv/cmd_buffer: Fix warning by initializing instance count. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
 2021-05-20 17:11:22 +00:00
Timur Kristóf 020c3c403f aco/util: Initialize IDSet::bits_set to zero. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
 2021-05-20 17:11:22 +00:00
Timur Kristóf c4f6e4d6b0 aco/insert_exec_mask: Fixed unused variable warning in release build. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
 2021-05-20 17:11:22 +00:00
Georg Lehmann 36d0ff4682 radv: Fix compatible image handle type for dmabufs. 
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 6c83e3ea98 ("radv: Add format modifier format queries.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10891>
 2021-05-20 15:11:07 +00:00
Samuel Pitoiset 489e38c708 radv: fix heap indices when computing the budget 
RADV_HEAP_* is the heap type, not the index.

Fixes dEQP-VK.info.device_memory_budget.

Fixes: 08d162f0b5 ("radv: expose 2/3rd of total memory as VRAM and 1/3rd as GTT on APUs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10852>
 2021-05-20 14:26:59 +00:00
Samuel Pitoiset b1171e5ffe Revert "radv: Do not access set layout during vkCmdBindDescriptorSets." 
This was a temporary workaround for a Baldur's Gate 3 bug which
should now be fixed.

This reverts commit eb104e949e.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3701
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10839>
 2021-05-20 13:38:33 +00:00
Samuel Pitoiset fe2a5716ee aco: fix derivatives/intrinsics with SGPR sources 
ds_swizzle_b32 requires a VGPR and DPP can't encode SGPR sources.

Fixes
dEQP-VK.graphicsfuzz.cov-derivative-uniform-vector-global-loop-count.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10840>
 2021-05-20 13:24:31 +00:00
Rhys Perry 3013670dfd aco: disallow SGPRs on DPP instructions 
They can't be encoded.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10841>
 2021-05-19 14:25:37 +00:00
Samuel Pitoiset 1bbbdfe590 radv: enable DCC stores on RDNA2 
It seems this gives 2-3% improvements most of the time. This also
enables DCC for concurrent images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10454>
 2021-05-19 07:17:29 +00:00
Bas Nieuwenhuizen c7904b5b9b aco: Implement bvh64_intersect_ray_amd intrinsic. 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10818>
 2021-05-18 23:02:25 +02:00
Bas Nieuwenhuizen 74d36c4f98 radv: Use correct border swizzle on GFX9+. 
We only need the format swizzle, not the full swizzle.

Fixes: 57e796a12a ("radv: Implement VK_EXT_custom_border_color")
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4020
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9731>
 2021-05-18 19:05:31 +00:00
Bas Nieuwenhuizen 07e0aab9d9 radv: Implement vkCmdTraceRays. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen 733c9b6d17 radv: Add RT pipeline bind. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen eba2b4137e radv: Add support for RT bind point. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen bf2b990618 radv: Use global BO list with raytracing. 
The shader binding tables in vkCmdTraceRays have no buffer reference.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen bfe2802188 aco: Add load_sbt_amd intrinsic implementation. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen 197d9f008e radv: Add sbt descriptors user SGPR input. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
 2021-05-18 18:29:36 +00:00
Timur Kristóf bc13049747 aco: Eliminate useless exec writes in jump threading. 
Eliminate exec writes which are unused by subsequent instructions.

Fossil DB results on Sienna Cichlid:

Totals from 80960 (54.03% of 149839) affected shaders:
CodeSize: 162953748 -> 161749372 (-0.74%)
Instrs: 31462273 -> 31161179 (-0.96%)
Copies: 2171239 -> 1942293 (-10.54%)
Branches: 807771 -> 807747 (-0.00%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
 2021-05-18 11:48:22 +00:00
Timur Kristóf e230dcc30b aco: Refactor SSA elimination phi info to use vector instead of map. 
No Fossil DB changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
 2021-05-18 11:48:22 +00:00
Timur Kristóf 25a7947da7 aco: Don't use s_and_saveexec with branches when exec is constant. 
When exec is constant, we can remember the constant as the old exec,
and just copy the condition and use it as the new exec. There is no
need to save the constant.

Due to using p_parallelcopy which is lowered to s_mov_b64 (or 32),
many exec restores now become copies, hence the increase in the copy
stats.

Fossil DB changes on Sienna Cichlid:

Totals from 73969 (49.37% of 149839) affected shaders:
SpillSGPRs: 1768 -> 1610 (-8.94%)
CodeSize: 99053892 -> 99047884 (-0.01%); split: -0.02%, +0.01%
Instrs: 19372852 -> 19370398 (-0.01%); split: -0.02%, +0.01%
VClause: 515154 -> 515142 (-0.00%); split: -0.00%, +0.00%
SClause: 719236 -> 718395 (-0.12%); split: -0.14%, +0.02%
Copies: 1109770 -> 1254634 (+13.05%); split: -0.07%, +13.12%
Branches: 374338 -> 374348 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1776481 -> 1653761 (-6.91%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
 2021-05-18 11:48:22 +00:00