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amd/registers: regenerate json files without 32-bit register fields

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Only a few of those were used in drivers.

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
This commit is contained in:
Marek Olšák
2021-05-07 04:09:16 -04:00
committed by Marge Bot
parent 72362f2830
commit ade5d9c2a7
9 changed files with 5599 additions and 16526 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/registers/gfx10.json
+939 -2678
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src/amd/registers/gfx103.json
+963 -2695
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src/amd/registers/gfx6.json
+605 -1880
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src/amd/registers/gfx7.json
+743 -2241
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src/amd/registers/gfx8.json
+754 -2278
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src/amd/registers/gfx81.json
+754 -2278
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src/amd/registers/gfx9.json
+835 -2465
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src/amd/vulkan/radv_sqtt.c
+3 -5
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@@ -66,8 +66,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c
cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE,
S_008D04_SIZE(shifted_size) | S_008D04_BASE_HI(shifted_va >> 32));
radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE,
S_008D00_BASE_LO(shifted_va));
radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_privileged_config_reg(
cs, R_008D14_SQ_THREAD_TRACE_MASK,
@@ -102,7 +101,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c
radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
S_030CDC_ADDR_HI(shifted_va >> 32));
radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, S_030CC0_ADDR(shifted_va));
radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, S_030CC4_SIZE(shifted_size));
@@ -128,8 +127,7 @@ radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *c
radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
S_030CD0_SH0_MASK(0xffff) | S_030CD0_SH1_MASK(0xffff));
radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2,
S_030CE0_INST_MASK(0xffffffff));
radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER, S_030CEC_HIWATER(4));
src/gallium/drivers/radeonsi/si_sqtt.c
+3 -6
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@@ -97,8 +97,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
S_008D04_SIZE(shifted_size) |
S_008D04_BASE_HI(shifted_va >> 32));
radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE,
S_008D00_BASE_LO(shifted_va));
radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
int wgp = first_active_cu / 2;
radeon_set_privileged_config_reg(cs, R_008D14_SQ_THREAD_TRACE_MASK,
@@ -134,8 +133,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
S_030CDC_ADDR_HI(shifted_va >> 32));
radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE,
S_030CC0_ADDR(shifted_va));
radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE,
S_030CC4_SIZE(shifted_size));
@@ -165,8 +163,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
S_030CD0_SH0_MASK(0xffff) |
S_030CD0_SH1_MASK(0xffff));
radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2,
S_030CE0_INST_MASK(0xffffffff));
radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER,
S_030CEC_HIWATER(4));