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7540 Commits

Author SHA1 Message Date
Timur Kristóf c850af936a aco: Remember when exec mask is const, and restore the const then. 
Previously, we would store even the constant -1 exec mask from the
beginning of every merged shader. With this change it is no longer
necessary because we can restore to constant exec mask directly.

Hence, this frees up a register pair (single register for Wave32)
in every merged shader.

No Fossil DB changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
 2021-05-18 11:48:22 +00:00
Timur Kristóf 04f90db9a0 aco: Use Operand instead of Temp for the exec mask stack. 
This will enable us to store non-temporary values,
such as constant operands there.

No Fossil DB changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
 2021-05-18 11:48:22 +00:00
Timur Kristóf 662bbf6ad4 aco: Determine whether a few more instructions need exec. 
These don't really need the exec mask (and never have), but we haven't
needed to include them in needs_exec_mask yet.

No Fossil DB changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
 2021-05-18 11:48:22 +00:00
Samuel Pitoiset 143c7f0375 radv: add missing entrypoints for VK_EXT_extended_dynamic_state2 
Fixes warnings with dEQP-VK.api.version_check.entry_points.

Fixes: d96507b73f ("radv: advertise VK_EXT_extended_dynamic_state2")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10831>
 2021-05-18 09:32:37 +00:00
Samuel Pitoiset 6d56c16c9c radv: dump the trap handler shader with RADV_DEBUG=metashaders 
Help debugging it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10656>
 2021-05-17 15:18:16 +00:00
Rhys Perry fb31dda909 aco/ra: use flags instead of booleans for update_renames() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10459>
 2021-05-17 13:31:07 +00:00
Rhys Perry 6fd6374e27 aco/ra: fix get_reg_for_operand() with vector operands 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10459>
 2021-05-17 13:31:07 +00:00
Rhys Perry c08bfa110c aco/ra: fix get_reg_for_operand() when the blocking var is a vector 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10459>
 2021-05-17 13:31:07 +00:00
Rhys Perry bc95d55e1f aco/ra: fix get_reg_for_operand() with no free registers 
fossil-db (Sienna Cichlid):
Totals from 195 (0.13% of 149839) affected shaders:
CodeSize: 2352160 -> 2356720 (+0.19%); split: -0.00%, +0.20%
Instrs: 431976 -> 433124 (+0.27%); split: -0.00%, +0.27%
Latency: 10174434 -> 10174897 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 4044388 -> 4044425 (+0.00%); split: -0.00%, +0.00%
Copies: 67634 -> 68762 (+1.67%); split: -0.00%, +1.67%

fossil-db (Polaris):
Totals from 186 (0.12% of 151365) affected shaders:
CodeSize: 2272356 -> 2276848 (+0.20%); split: -0.00%, +0.20%
Instrs: 432390 -> 433513 (+0.26%); split: -0.00%, +0.26%
Latency: 13153394 -> 13160194 (+0.05%); split: -0.00%, +0.05%
InvThroughput: 10889509 -> 10889967 (+0.00%); split: -0.00%, +0.00%
SClause: 12745 -> 12747 (+0.02%)
Copies: 74832 -> 75945 (+1.49%); split: -0.01%, +1.50%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10459>
 2021-05-17 13:31:07 +00:00
Rhys Perry 4e459df0fc aco/ra: initialize temp_in_scc earlier 
We need to know if there's a temporary in SCC before the instruction, not
after.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa78 ("aco: Initial commit of independent AMD compiler")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10459>
 2021-05-17 13:31:07 +00:00
Daniel Schürmann b960169257 aco/ra: also prevent overflow register for p_create_vector operands 
Fixes: d659ce0d6c ('aco/ra: prevent underflow register for p_create_vector operands')
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10832>
 2021-05-17 11:18:25 +00:00
Rhys Perry dc525cbe0c ci: remove expected robustness2 fails for Renoir 
These should be fixed now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Fixes: 157c6b0f33 ("radv,aco: use per-attribute vertex descriptors for robustness")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10834>
 2021-05-17 11:06:36 +00:00
Connor Abbott a40714abf7 nir/lower_phis_to_scalar: Add "lower_all" option 
We don't want to have to deal with vector phis in freedreno, because
vectors are always split/unsplit around vectorized instructions anyways,
and the stated reason for not scalarising them (it hurting coalescing)
won't apply to us because we won't be using nir_from_ssa. Add this
option so that we don't have to do the equivalent thing while
translating from NIR.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10809>
 2021-05-17 09:59:45 +00:00
Joshua Ashton 855cb78d46 radv: Handle unnormalized samplers in YCbCr lowering 
We need to divide these by their divisors and special-case COSITED_EVEN.

Fixes NV12 compositing in Gamescope.

Fixes: 91702374 ("radv: Add ycbcr lowering pass.")
Cc: mesa-stable
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10816>
 2021-05-15 18:15:52 +00:00
Daniel Schürmann b3eb87aa65 radv: call nir_copy_prop() after load-store vectorization 
The load-store vectorizer can create a large amount
of unnecessary nir_op_vec and nir_op_mov instructions.
This prevents nir_opt_move from stalling to much and
potentially also helps other passes.

Closes: #4778
Fixes: 1958381c9a ('radv: Reorder some NIR optimizations in preparation for the I/O changes.')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10804>
 2021-05-14 17:38:46 +00:00
Daniel Schürmann d659ce0d6c aco/ra: prevent underflow register for p_create_vector operands 
It could happen that we tested negative out-of-range
registers for p_create_vector operands resulting in a crash.

Fixes: 8962510e38 ('aco/ra: Conservatively refactor get_reg_specified to use PhysRegInterval')
Closes: #4697
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10799>
 2021-05-14 17:26:41 +00:00
Tony Wasserka 80ee9d3947 aco/scheduler: Verify register demand invariants in debug mode 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
 2021-05-13 15:27:57 +00:00
Tony Wasserka 50ba919d37 aco/scheduler: Fix register demand computation for upwards moves 
The initial value needs to be taken from the instruction that is being
moved over, not the one to be moved.

Additionally the parameter of this function was removed because it was
misleading. Setting it to any value other than source_idx would cause
register_demand to be initialized incorrectly. (Instead, the maximum
demand among the covered instructions would need to be determined.)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
 2021-05-13 15:27:57 +00:00
Tony Wasserka c528af1076 aco/scheduler: Fix register demand computation for downwards moves 
Previously, changes in total_demand_clause were not always propagated to
total_demand. For instance, clause moves do not change the local register
demand at the end of a clause, yet they may still affect the total maximum.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 8235bc6411 ("aco: try to group together VMEM loads of the same resource")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4533
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
 2021-05-13 15:27:57 +00:00
Daniel Schürmann c7d679f0f7 aco: relax validation rules for p_reduce dst RegType 
By exposing a subgroupSize of 64, reductions with
cluster_size 32 in wave32 might be considered divergent,
and thus, result in a VGPR.

Fixes: dEQP-VK.subgroups.clustered.graphics.subgroupclustered* with wave32

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10769>
 2021-05-13 15:10:24 +00:00
Daniel Schürmann 989e9867a6 aco: fix additional register requirements for spilling 
It could happen that VGPR spilling without SGPR spilling
calculated a negative spills_to_vgpr number and then
increasing the VGPR target demand above the limit.

Cc: mesa-stable

Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10756>
 2021-05-12 14:13:24 +00:00
Timur Kristóf bb127c2130 radv: Use new NIR lowering of NGG GS when ACO is used. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 60ac5dda82 ac: Add NIR lowering for NGG GS. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 9732881729 radv: Use new NGG NIR lowering for VS/TES when ACO is used. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 3d589b8b46 ac: Add new NIR pass to lower NGG VS/TES. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 89a76ff786 aco: Implement new NGG specific NIR intrinsics. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 33e29f8f9b radv: Gather NGG info sooner. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 1630ec96d3 radv: Fill shader info earlier. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 75a002f809 aco: Split ngg_emit_sendmsg_gs_alloc_req from the wave0 check. 
This allows us to emit the gs_alloc_req independently of the
wave ID check, which is what the NIR lowering will need.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf ad8dd39bd3 aco: Fixup the NIR metadata after sanitize_cf_list. 
sanitize_cf_list can in fact invalidate the dominance metadata,
which we need to use eg. nir_unsigned_upper_bound.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Timur Kristóf 00fd087f0a aco: Allow workgroup barrier and shared scope for NGG shaders. 
NGG already needs to use workgroup barriers, but this commit allows
them to come from NIR as opposed to just emitting it in ACO
instruction selection.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
 2021-05-12 13:47:04 +00:00
Tomeu Vizoso 8b04b77118 ci: Remove the need for an empty Piglit results file 
Just create such an empty file if there isn't already.

So drivers that are expected to pass all tests don't need to commit an
empty results file.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10295>
 2021-05-11 20:07:29 +00:00
Simon Ser 0e94675494 radv: stop special-casing multi-planar formats in radv_get_modifier_flags 
In radv_get_modifier_flags, we had a special case for multi-planar
formats. However ac_is_modifier_supported should already take care of
rejecting unsupported modifiers for multi-planar buffers.

Some time ago, ac_is_modifier_supported rejected any non-linear modifier
for multi-planar formats. 35e25ea1d0 ("ac/surface: allow non-DCC modifiers
for YUV on GFX9+") changed that to allow non-DCC modifiers with
multi-planar formats on GFX9+. Since then, the radv check has been out
of sync.

A similar patch was applied to radeonsi in 979e138695 ("radeonsi: stop
special-casing YUV formats in si_query_dmabuf_modifiers").

This fixes tiling artifacts with NV12 buffers.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10623>
 2021-05-10 14:31:21 +00:00
Rhys Perry a54f111831 radv,aco: compact vertex buffer descriptors 
It seems common for there to be holes.

fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 33791 (23.10% of 146267) affected shaders:
(no statistics changed)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
 2021-05-10 12:09:14 +00:00
Rhys Perry 20a0744e22 Revert "radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2" 
This reverts commit a8a6b9fb2fdcb1bea55707fa0c2b8e96f03c6b5b.

This is no longer necessary now that we fixup the size when creating the
descriptors.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
 2021-05-10 12:09:14 +00:00
Rhys Perry 157c6b0f33 radv,aco: use per-attribute vertex descriptors for robustness 
We have to use a different num_records for each attribute to correctly
implement robust buffer access.

fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 60059 (41.06% of 146267) affected shaders:
VGPRs: 2169040 -> 2169024 (-0.00%); split: -0.02%, +0.02%
CodeSize: 79473128 -> 81156016 (+2.12%); split: -0.00%, +2.12%
MaxWaves: 1635360 -> 1635258 (-0.01%); split: +0.00%, -0.01%
Instrs: 15559040 -> 15793205 (+1.51%); split: -0.01%, +1.52%
Latency: 90954792 -> 91308768 (+0.39%); split: -0.30%, +0.69%
InvThroughput: 14937873 -> 14958761 (+0.14%); split: -0.04%, +0.18%
VClause: 444280 -> 412074 (-7.25%); split: -9.22%, +1.97%
SClause: 588545 -> 644141 (+9.45%); split: -0.54%, +9.99%
Copies: 1010395 -> 1011232 (+0.08%); split: -0.44%, +0.53%
Branches: 274279 -> 274282 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1431171 -> 1405056 (-1.82%); split: -2.89%, +1.07%
PreVGPRs: 1575253 -> 1575259 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
 2021-05-10 12:09:14 +00:00
Rhys Perry dfa38fa0c7 aco: group loads from the same vertex binding into the same clause 
In the future, we might have vertex attribute loads from the same binding
but with different descriptors. Since they will be loading from the same
buffer, we should continue grouping them into clauses.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
 2021-05-10 12:09:14 +00:00
Timur Kristóf 4bb2e42fb4 radv: Properly enable Wave32 mode for NGG GS. 
The condition for enabling it was incorrect, and was always false.
Therefore, it was never really enabled.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10683>
 2021-05-10 11:39:23 +00:00
Timur Kristóf 925bd5f990 radv: Ignore GS copy shader when determining NGG GS wave size. 
The GS copy shader is not used with NGG GS.
This fixes a big bug when NGG GS is running in Wave32 mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10683>
 2021-05-10 11:39:23 +00:00
Samuel Pitoiset 54b0cfb061 radv: fix extending the dirty bits to 64-bit 
New dynamic states added for VK_EXT_extended_dynamic_state2 causes
GPU hangs with vkd3d-proton.

Fixes: 7bdd569d7e ("radv: extend the dirty bits to 64-bit")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10693>
 2021-05-07 18:09:00 +00:00
Samuel Pitoiset d96507b73f radv: advertise VK_EXT_extended_dynamic_state2 
This only implements dynamic primitive restart enable, depth bias
enable and rasterizer discard enable. I leave logic op and patch
control points for later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:59 +00:00
Samuel Pitoiset dd19bf9d7d radv: implement dynamic rasterizer discard enable 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:59 +00:00
Samuel Pitoiset c40d7fadc3 radv: implement dynamic primitive restart enable 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:59 +00:00
Samuel Pitoiset f2933e9872 radv: implement dynamic depth bias enable 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:58 +00:00
Samuel Pitoiset 44e7bcf942 radv: declare new dynamic states for VK_EXT_extended_dynamic_state2 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:58 +00:00
Samuel Pitoiset c4a639238e radv: declare VK_EXT_extended_dynamic_state2 but leave it disabled 
To declare new prototypes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:58 +00:00
Samuel Pitoiset 33ede796d5 radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE 
To make them readable by shaders, only needed on GFX10+.

This also fixes corruption with Control and MSAA.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10610>
 2021-05-06 06:30:05 +00:00
Samuel Pitoiset 08d162f0b5 radv: expose 2/3rd of total memory as VRAM and 1/3rd as GTT on APUs 
A bunch of games complain when the VRAM size is too small. The most
compatible solution seems to return memory heaps like a dGPU.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3423
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>
 2021-05-05 08:44:17 +02:00
Samuel Pitoiset 986a3243cf radv: adjust the computation of the total usage of memory used 
internal_usage is the memory allocated by the current process (intent)
while system_usage is the memory allocated globally (actual).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>
 2021-05-05 08:44:17 +02:00
Caio Marcelo de Oliveira Filho dd48683cfd nir: Move shared_memory_explicit_layout bit into common shader_info 
Move it out of the "cs" sub-struct, since the bit can be used for
other shader stages in the future.

This also removes a subtle issue in spirv_to_nir:
info.cs.shared_memory_explicit_layout was used without checking for
the CS shader stage.  It ended up being "harmless" since the effects
also depended on presence of shared variables.

Fixes: 5de6c5973a ("spirv: Implement SPV_KHR_workgroup_memory_explicit_layout")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10529>
 2021-05-04 20:54:58 +00:00