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Author SHA1 Message Date
Rhys Perry b634d7f3e2 nir/opt_vectorize: fix srcs_equal() with two different non-const 
To match hash_alu_src(), this should return false if both are different
non-const ssa defs.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8391>
 2021-01-09 11:14:05 +00:00
Rhys Perry bdf316ae7b nir/opt_vectorize: fix typo in instr_can_rewrite() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8391>
 2021-01-09 11:14:05 +00:00
Mauro Rossi e7444bd3a6 android: ac/radv: fix typo in ac_rgp.h listed in Makefile.sources 
Fixes the following building error:

error: external/mesa/src/amd/Android.mk: libmesa_amd_common: Unused source files: common/ac_rgph.

Fixes: 4ec5cf5318 ("ac/radv: move radv_rgp.c to ac")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8371>
 2021-01-09 11:15:09 +01:00
Marek Olšák be50c7f329 gallium/u_threaded: skip draws if user index buffer size has size == 0 
This happens when all draws have count == 0.

Fixes: 85b6ba136b "st/mesa: implement Driver.DrawGallium callbacks

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8345>
 2021-01-09 06:53:00 +00:00
Marek Olšák c69b8fd651 vbo: fix a index buffer map failure with size = 0 in get_minmax_indices_gallium 
Fixes: 85b6ba136b "st/mesa: implement Driver.DrawGallium callbacks

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8345>
 2021-01-09 06:53:00 +00:00
Marek Olšák 3c75473525 mesa: skip draws w/ count == 0 and instance_count == 0 in draw_gallium_fallback 
Fixes: 85b6ba136b "st/mesa: implement Driver.DrawGallium callbacks

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8345>
 2021-01-09 06:53:00 +00:00
Marek Olšák 8fc6a19765 gallium: skip draws with count == 0 or instance_count == 0 in drivers 
Fixes: 85b6ba136b "st/mesa: implement Driver.DrawGallium callbacks"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8345>
 2021-01-09 06:53:00 +00:00
nia 275079e3ad util: Avoid pthread_setaffinity_np on NetBSD 
NetBSD's variant has a different prototype from the Linux version
the code expects. It might make sense to add support for NetBSD's
version, however, since NetBSD defaults to not allowing non-root
users to set processor affinity, there would be little gain here.

This is a build fix for NetBSD.

Signed-off-by: Nia Alarie <nia@NetBSD.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
CC: 20.3 <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7947>
 2021-01-09 06:22:13 +00:00
Vinson Lee 5c59e4efe2 clover: Add constructor for clover::module. 
Fix defect reported by Coverity Scan after commit 95527fe229
("clover/module: add a printf support to module (v5)").

Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value
m.printf_strings_in_buffer when calling module.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8322>
 2021-01-08 18:28:43 -08:00
Nanley Chery fb4e67df1e iris: Drop fast_clear_color's blorp_flags param 
Now that conditional fast clears are disabled, the blorp_flags parameter
is unused.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7762>
 2021-01-08 23:23:31 +00:00
Nanley Chery 04ac3a6620 iris: Delete iris_resolve_conditional_render 
This function has no more users.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7762>
 2021-01-08 23:23:31 +00:00
Nanley Chery c3785c0c9d iris: Disable conditional fast clears 
For color buffers, conditional fast clears can cause aux-state tracking
to lose information necessary for resolves later on.

For depth buffers, they never actually worked because they occurred
unconditionally. Even if they were conditional, they would suffer from
the same issues as color buffers.

Enables iris to pass the nv_conditional_render-clear-bug piglit test.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3565
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7762>
 2021-01-08 23:23:31 +00:00
Nanley Chery b12b69b04b iris: Make can_fast_clear_depth return constants 
Make can_fast_clear_depth more consistent with can_fast_clear_color.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7762>
 2021-01-08 23:23:31 +00:00
Nanley Chery fc06683d07 iris: Explain how conditional aux accesses work 
Apart from an issue with fast clears that will be addressed soon,
aux-state tracking with conditional rendering works because the
aux-state info needed for performing required resolves is never lost.

Add comments explaining how this works. Assertions are omitted to avoid
having to pass render_condition variables into
iris_resource_prepare_access and iris_resource_finish_write.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7762>
 2021-01-08 23:23:31 +00:00
Jason Ekstrand 2d08711a2c anv: Bump maxGeometryInputComponents to 128 on Gen8+ 
See 8e627af59d and 1e3e72e305 for why this may not be a good
idea on Gen7.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8397>
 2021-01-08 23:17:26 +00:00
Eric Anholt 670944ba04 nir/lower_locals_to_regs: Use the imul_imm helper instead of forcing it. 
Cleaned up a bit of addressing math in the shader I just had to debug.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt 111e4be698 gallium/ntt: Work around virglrenderer UIF handling bug. 
Until just recently ("vrend: Fix TGSI UIF/IF behavior"), virgl does "if
(any(bvec4(src0)))" instead of "if (src0.x != 0)", despite the tgsi.rst
documentation and tgsi_exec agreeing on the second form.  It's harmless to
work around it, since apparently NTT was the only one to not have scalar
swizzled the if condition.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt 470d806cc2 gallium/ntt: Drop comment about needing array_id for svga tess. 
The svga tess stuff is about internally making a temp array, not arrayid
of the outputs.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt 67c5db9b9f gallium/ntt: Drop comment about needing loop label setup. 
BRK/CONT don't take a label, as shown by tgsi_opcode_tmp.h and the lack of
any users of a label on those instructions in tree.  I can't find any user
of ENDLOOP's label.  Additionally, GLSL-to-TGSI apparently never set up
the BGNLOOP label, so even nvfx's usage probably wants us to not set it.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt 4538ebb8f9 gallium/ntt: Add support for emitting TXF_LZ. 
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt c6d3fd8c21 gallium/ntt: Emit sample index when necessary for image load/store. 
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt 30c797a0df gallium/ntt: Emit SSBO buffer declarations. 
This doesn't set the atomic flag the way the old TGSI path used to,
leaving us with a possible delta in caching modes on nv50 tgsi.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:31 +00:00
Eric Anholt e58baeeaef gallium/ntt: Drop XXX comment about supporting carry opcodes. 
The GLSL-to-NIR path didn't do carry, so we don't need to.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8373>
 2021-01-08 21:04:30 +00:00
Eric Anholt ff67898daf ci: Disable the freedreno farm, which went down last night. 
We're debugging it now, but let merges flow until then.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8395>
 2021-01-08 19:21:09 +00:00
Ilia Mirkin c0171c4626 nv50: fake enough resume support pre-nva0 to pass gles3 requirements 
GLES3 supports pause/resume of xfb. However since there's no geometry
shader support in ES3, it's a lot easier to figure out the offsets to
use. This makes it work for the dEQP tests at least.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8346>
 2021-01-08 13:43:12 -05:00
Ilia Mirkin e0a2af3325 nv50: only support 4 components in separate xfb mode 
This is consistent with what the blob reports.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8346>
 2021-01-08 13:40:52 -05:00
Chia-I Wu 2b08dfbb69 virgl: fix modifier truncation 
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8372>
 2021-01-08 09:51:06 -08:00
Rhys Perry f01bca8100 radv/winsys: set has_packed_math_16bit in null winsys 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8392>
 2021-01-08 16:16:19 +00:00
Erik Faye-Lund 6f3a34e75c microsoft/compiler: do not lower away 64-bit ffma 
In DXIL, the FMA instruction only supports 64-bit operations. However,
back when we implemented support for this, there were only a single
switch for lowering all ffma instructions, so we couldn't easily use it.

But now that there's separate flags to lower ffma on 16, 32 and 64 bit,
we can lower 16 and 32 bit ffmas, and leave 64 bit ffmas alone.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8349>
 2021-01-08 15:09:23 +00:00
Erik Faye-Lund c2fa965cc3 microsoft/compiler: correct dxil fma opcode 
When I originally added the FFMA opcode here, I added the FMAD opcode
instead of the FMA opcode. The reason for this is that it works on
32-bit values as well, so that seemed like a better fit.

But that's not correct, as the FMA opcode isn't a fused operation, so
let's correct the opcode.

This isn't currently in use, because we currently lower away all ffma
opcodes on the NIR level, but that's about to change.

While we're at it, let's also update the opcode name to match the DXIL
documentation.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8349>
 2021-01-08 15:09:23 +00:00
Erik Faye-Lund 317ec8b501 zink: disable render_condition_enable during blit 
We don't support stencil-exports yet, and even when we will, we might
not support it on all hardware. So we really need an alternative plan
here, even when render_condition_enable is true.

Fixing this properly is much more involved, and depends on reworking
render-condition along the lines that we do in !7746 to support pausing
and resuming properly first. So let's do the minimal thing, which is to
allow this to work in cases where no render-condition is active.

Fixes: 767f70dfe1 ("gallium/util: fix util_can_blit_via_copy_region for conditional rendering")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4056
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8379>
 2021-01-08 15:03:44 +00:00
Simon Ser 7ef2046065 radv: only set BO metadata for the first plane 
To properly support multi-planar images, we don't want to set metadata
on anything other than the first plane. To achieve this radv currently
checks for the image TILING and assumes LINEAR means it's not the first
plane.

However this doesn't account for images with a single LINEAR plane. We
still want to set metadata on those, e.g. to properly set the scanout
bit in the tiling flags.

Instead of checking for LINEAR, check if the offset is zero. Only the
first plane has a zero offset on AMD.

This mirrors the radeonsi logic [1].

While at it, move the metadata declaration into the if block.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/blob/6fecdc6dda6da15d616a31900508214c81cd256e/src/gallium/drivers/radeonsi/si_texture.c#L710

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8086>
 2021-01-08 14:52:18 +00:00
Mike Blumenkrantz 4e3e7f35f7 zink: clamp shader input/output max values 
some vulkan drivers (e.g., amdvlk) advertise absolutely huge values here,
resulting in bitmask overflows everywhere since gallium assumes a max of
32 for vertex inputs and nir uses 64bit types for others

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8318>
 2021-01-08 14:44:31 +00:00
Rhys Perry d95fe8a25e radv: support SpvCapabilitySparseResidency 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 4c67423e99 radv: implement is_sparse_texels_resident and sparse_residency_code_and 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 6d5e26752c ac/nir: implement sparse image/texture loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 55aeac7af4 ac/nir: implement nir_op_vec5 
Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry a502aa7b04 aco: form sparse load clauses 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 0bd14be962 aco: implement sparse image loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 382f50ad2c aco: implement sparse texture fetches 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 5a4f6313b1 aco: implement nir_op_vec5 
Since sparse fetch/load uses vec5 destinations, it may be possible that we
encounter nir_op_vec5.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 962c917cea aco: move MIMG VDATA to its own operand 
We will want both a VDATA operand and a sampler for some TFE/LWE MIMG
instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 2aaf52bb85 aco: fix MIMG_instruction::lwe comment 
The ISA docs were inconsistent about what this flag does, but that seems
fixed in the RDNA doc.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
 2021-01-08 14:27:07 +00:00
Rhys Perry 816b7fb5cb aco: fix unreachable() for uniform 8/16-bit nir_op_mov from VGPR 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: d20a752c0d ("aco: use Builder::copy more")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8380>
 2021-01-08 12:54:36 +00:00
Michel Dänzer 10431c8964 ci: Add *ignore_scheduled_pipelines to mesa/gallium rules templates 
These are currently not used directly, but maybe this can prevent copy
and paste accidents.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8360>
 2021-01-08 09:57:21 +00:00
Michel Dänzer 6bde5cf276 ci: Rule out scheduled pipelines in .windows-build-rules 
The lack of this broke scheduled pipelines, because they attempted
to create a meson-windows-vs2019 job, which couldn't work (because the
windows_build_vs2019 job doesn't exist in scheduled pipelines).

Fixes: 84c8a35aa2 "CI: Add Windows source dependency map"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8360>
 2021-01-08 09:57:21 +00:00
James Park 3fb4755d48 util: Disable memstream for Apple builds 
Not all SDK versions support open_memstream. Maybe some other day.

Fixes: af8d488ea5 ("util,ac,aco,radv: Cross-platform memstream API")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8269>
 2021-01-08 09:37:14 +00:00
Samuel Pitoiset f40a7d3c93 radv: fix performance regression by restoring TC-compat HTILE in GENERAL 
This fixes a performance regression for games (eg. Youngblood) that
declare all images as concurrent. This is likely buggy for compute
queues but this just restores the previous behaviour for now.

Fixes: f4f096805b ("radv: fix TC-compat HTILE images with DST_OPTIMAL on the compute queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8351>
 2021-01-08 09:22:32 +00:00
Samuel Pitoiset 0ae1cf46a6 radv: fix enabling TC-compat HTILE in GENERAL for writes on GFX10+ 
It wasn't expected to also enable inside render loops.

Fixes: 4bb92d9145 ("radv: enable TC-compat HTILE in GENERAL on GFX10+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8351>
 2021-01-08 09:22:32 +00:00
Samuel Pitoiset 20683461e3 radv: configure the texture descriptor for TC-compat CMASK on GFX10+ 
This was missing, it can be enabled with RADV_PERFTEST=tccompatcmask.
Note that this feature is still experimental.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8350>
 2021-01-08 08:21:17 +01:00