Commit Graph

12799 Commits

Author SHA1 Message Date
Carlos Santa 39e3015c36 intel/hang_replay: remove EXEC_OBJECT_WRITE
This flag causes the following failure:

total_vma: 0x0000000071c9d000
fail to set context hw img: Invalid argument

Fixes: bab52763f4 ("intel/hang_replay: fix batch address")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11959
Signed-off-by: Carlos Santa <carlos.santa@intel.corp-partner.google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31494>
2024-10-04 21:37:41 +00:00
Carlos Santa 700141da43 intel/hang_replay: fix the typo in the ioctl call
What we really want to pass is DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
vs DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM

Fixes: a9f1151de2 ("intel/hang_replay: use hw image param")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11959
Signed-off-by: Carlos Santa <carlos.santa@intel.corp-partner.google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31494>
2024-10-04 21:37:41 +00:00
Mike Blumenkrantz 5ba00df1f9 anv: add VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16 to modifier exceptions
this is implemented

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31516>
2024-10-04 13:22:08 +00:00
Danylo Piliaiev e5d3eba096 u_trace: Fix trace_payload_as_extra_func desync between drivers
Buffer with indirect args wasn't passed to the function which
adds extra event args. Since function definition depends on the
common code, the definition is moved to a single place.

Fixes: 0a17035b5c
("u_trace: add support for indirect data")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31090>
2024-10-03 20:25:48 +00:00
Nanley Chery 26692deefc anv: Delete stale comment for BLORP clear color addr
It looks like this comment attempted to describe all the reasons we need
to pass the clear color address to BLORP. This comment actually isn't
exhaustive and some bits are out of date (e.g., BLORP no longer updates
the clear color address for us). Let's just delete it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery 10bcfb63d5 anv: Prevent clear color modifier corruption with views
If a dmabuf is shared with a clear color, the raw clear color channels
generally won't be interpreted correctly during format reinterpretation.
So, prevent Vulkan apps from trying to use such dmabufs as mutable
format render targets. Also, prevent such apps from using such dmabufs
as blorp_copy() destinations if doing so would require format
reinterpretation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery edfb33efdd intel/blorp: Use original surface format for some copies
In iris, this should avoid some partial resolves when copying between
images. In anv, this will reduce restrictions on dmabufs which have
clear color support in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery 73637dbce4 intel/blorp: Choose some copy formats independently
blorp_copy_get_formats() tries to make the source and destination view
formats match as much as possible. This avoids some casting in the copy
shader, but it makes determining the format that will be used for a
surface impossible without having the ISL surface for both that surface
and a source or destination.

We'd like to enable the Vulkan driver to know as early as possible what
format an image may be reinterpreted as for correctness. So, determine
the copy formats more independently and expose a helper which does so
for drivers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery 6721064939 anv: Use image formats when copying to/from buffers
blorp_copy() will sometimes use a complex shader if the source and
destination surface formats differ. For example, it will do this when
both formats support CCS_E, but have differing numbers of
bits-per-channel.

To reduce the chance of using this complex shader during transfers
between images and buffers, ensure the same format is used. We can't
completely prevent the complex shader because a copy may happen between
surface formats that have a different number of bits-per-pixel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Tapani Pälli ac00d97e31 anv: use mi_builder in CmdBeginTransformFeedbackEXT
Patch converts MI_LOAD_REGISTER_MEM, MI_LOAD_REGISTER_IMM to use
mi_builder in CmdBeginTransformFeedbackEXT.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31502>
2024-10-03 16:20:40 +00:00
Lionel Landwerlin 1f2ad64b63 anv: optimize WA 16011107343/22018402687
No need to emit the instruction twice.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31481>
2024-10-02 17:27:55 +00:00
Lionel Landwerlin 4cdb5de163 anv: consolidate pre/post draw workaround in helpers
This avoids sprinkling those all over the code base. Debug breakpoints
are put in there too.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31481>
2024-10-02 17:27:55 +00:00
Lionel Landwerlin 18e2c25dad anv: limit 22018402687 to impacted platforms
ARL is impacted, but LNL is not.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31481>
2024-10-02 17:27:55 +00:00
Caio Oliveira 366f63fd88 intel/brw: Enable mi_builder test for Xe2
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299>
2024-10-01 16:03:35 -07:00
Caio Oliveira a0ea2a656f intel/brw: Enable EU validation and compaction tests for Xe2
A few EU validation tests had to be updated to account for larger GRF,
extra supported types for 3-src instructions and the lack of AccWrEnable
in Xe2.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299>
2024-10-01 16:03:35 -07:00
Caio Oliveira 8b1c5425a9 intel/brw: Update DPAS validation tests for Xe2
The main change is that in Xe2 DPAS instruction requires SIMD16.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299>
2024-10-01 16:03:35 -07:00
Lionel Landwerlin ee738c523a isl/tests: split linear & tiled buffer sizes
There is this weird thing in the current tests that the linear & tiled
buffers are sized the same.

They don't need to be, compute a max area we want to check (aligned to
a tile logical size), allocate the linear buffer using that aligned
size and allocate the tiled buffer using a size aligned to the
physical tile size.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin d8da594a60 isl/tests: rename tile_(width|height) variables
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 05b641becc isl/tests: add TileX memcpy testing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 2994eca831 isl/tests: fix inclusive coordinate checking
The coordinates are supposed to be inclusive.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 0b22d43f86 isl/tests: use modulo for more variability per pixel
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin e80a02f52d isl/tests: bump coordinate types to 32bits
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 451b9e6850 isl/tests: rename ytile to be consistent with other names
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 25d6b47298 isl/tests: fix coordinates for comparison scan
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 3384179e26 isl/tests: fixup multi-tile testing
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin 86900e3cf6 isl/tests: add a space in memcpy test error printouts
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Lionel Landwerlin b2b654d851 isl: fix comment typo
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31469>
2024-10-01 22:26:44 +00:00
Caio Oliveira b4acc3fc42 intel/brw: Remove Gfx8- from test_eu_validate.c
These tests only run for Gfx9+.

Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31272>
2024-10-01 21:16:54 +00:00
Samuel Pitoiset e120176c58 ci: uprev VKCTS to 1.3.9.2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31423>
2024-10-01 17:30:38 +00:00
Lionel Landwerlin 17c3bd358e anv: limit render target cache flushing due to color output remapping
Fixes a performance regression of 1%/2% introduced in badb3f6301
("anv: Only flush render target cache when detecting RT changes")

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31380>
2024-10-01 15:52:39 +00:00
Hyunjun Ko f76781feb8 anv: enable KHR_video_maintenance1
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
2024-10-01 10:45:14 +09:00
Hyunjun Ko ac2fd8ae66 anv: support VK_IMAGE_CREATE_VIDEO_PROFILE_INDEPENDENT_BIT_KHR
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
2024-10-01 10:45:14 +09:00
Hyunjun Ko 0981d20850 anv: support for inline query for vulkan video
v1. Removed the unnecessary query begin code.
(lionel.g.landwerlin@intel.com)

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
2024-10-01 10:45:14 +09:00
Hyunjun Ko 1b06d4a8ea anv: consider VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR when
allocating mv storgae.

Fixes: 3ec8f7f99 ("anv/video: initial support for h264 encoding")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
2024-10-01 10:45:14 +09:00
Hyunjun Ko 8a3f852119 anv/video: support VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DISABLED_BIT_KHR.
Which means to support CQP mode.

Fixes: 3ec8f7f99 ("anv/video: initial support for h264 encoding")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31436>
2024-10-01 10:45:14 +09:00
Jules Blok 4994c5a243 anv: Add support for VK_EXT_depth_clamp_control
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31411>
2024-09-30 22:18:27 +00:00
Paulo Zanoni bd33917509 anv: remove another copy of the texture cache pipe_control workaround
The workaround is already implemented by
batch_emit_pipe_control_write(), we don't need to do it here as well.

This was spotted by Lionel Landwerlin. The credits go to him, I just
wrote the patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31412>
2024-09-30 21:44:12 +00:00
Paulo Zanoni fd4a44430c anv: remove duplicate pipe_control workaround
Commit a603cc0633 ("anv: move some pc was to
batch_emit_pipe_control_write") moved some WAs from
emit_apply_pipe_flushes() to batch_emit_pipe_control_write(), but it
turns out one of them was already there since cf7e1f3817 ("anv,
iris: add missing CS_STALL bit for GPGPU texture invalidation").

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31412>
2024-09-30 21:44:12 +00:00
Tapani Pälli c1a44e8d43 anv: force StackIDControl value for Wa_14021821874
This is also encouraged by another wa, Wa_14018813551.

Both workarounds state that StackIDControlOverride_RTGlobals should
always be set to 0 (i.e. 2k).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30937>
2024-09-30 07:33:37 +03:00
Mike Blumenkrantz 3178170516 ci: bump gl cts versions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31118>
2024-09-29 12:18:49 +00:00
Guilherme Gallo d801c1101d ci/anv: Update xfiles
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31414>
2024-09-27 16:38:27 +00:00
Guilherme Gallo a748d38ec9 ci/anv: Introduce missing farm var for ADL jobs
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31414>
2024-09-27 16:38:27 +00:00
Guilherme Gallo a06102ca6c ci/intel: Rebalance jobs via parallel
Take advantage of 3 spare JSL in Collabora lab to load the balance of
those jobs:

job name	avg duation (min)

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
---		---
anv-jsl		15
anv-jsl-angle	20
iris-jsl-deqp	18

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31414>
2024-09-27 16:38:26 +00:00
Sviatoslav Peleshko 57344052b6 intel/brw: Don't apply discard_if condition opt if it can change results
We can't just always negate the alu instruction's cmod, because negating
it can produce different results when the argument is NaN float. We can
still do that if the condition is == or !=.

Fixes: 0ba9497e ("intel/fs: Improve discard_if code generation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11800
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31042>
2024-09-27 11:52:27 +00:00
Caio Oliveira 93c3780bc1 intel/brw: Skip per-primitive inputs when computing flat input mask
The per-primitive have their own separate section in the FS thread
payload, and are not considered when setting the mask in
3STATE_SBE's ConstantInterpolationEnable.

This is also consistent with what is done for brw_interp_reg().

Fixes
- dEQP-VK.mesh_shader.ext.misc.clip_geom_provoking_last
- dEQP-VK.mesh_shader.ext.misc.clip_geom_and_task_shader_provoking_last

Backport-to: 24.2
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11844
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31417>
2024-09-27 08:15:18 +00:00
Iván Briano a4cbc903a8 anv: allocate sparse descriptor buffers from the correct heap
When allocating a buffer normally, this flag gets to the allocator from
the memory requirements, but when sparse bindings are created we were
checking for them but never setting them.
Fixes sparse descriptor buffers on Xe2.
Makes the failure on TRTT more obvious.

Fixes: c6a91f1695 ("anv: add new heap/pool for descriptor buffers")
Fixes: 692e1ab2c1 ("anv: get rid of the second dynamic state heap")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31372>
2024-09-27 04:49:22 +00:00
Paulo Zanoni fe59044f47 anv/trtt: mark vk_sync_get_value()'s value as defined for Valgrind
Valgrind doesn't seem to know that drmSyncobjQuery() writes to the
variable that we pass as 'last_value'. This gets rid of:

==6275== Conditional jump or move depends on uninitialised value(s)
==6275==    at 0x5308370: anv_sparse_trtt_garbage_collect_batches (anv_sparse.c:540)
==6275==    by 0x53091E2: anv_sparse_bind_trtt (anv_sparse.c:825)
==6275==    by 0x5309771: anv_sparse_bind (anv_sparse.c:953)
==6275==    by 0x5309A3B: anv_free_sparse_bindings (anv_sparse.c:1041)
==6275==    by 0x529FF21: anv_DestroyBuffer (anv_buffer.c:248)
==6275==    by 0x932ADBD: ??? (in /usr/lib/x86_64-linux-gnu/libVkLayer_khronos_validation.so)
==6275==    by 0x127AA2: MyVkBuffer::~MyVkBuffer() (sparse.cpp:364)
==6275==    by 0x12B2D4: MyApp::test1_trivial_sparse() (sparse.cpp:1421)
==6275==    by 0x13E01A: MyApp::run_test(int) (sparse.cpp:6594)
==6275==    by 0x13E3B0: main (sparse.cpp:6656)
==6275==  Uninitialised value was created by a stack allocation
==6275==    at 0x53082D3: anv_sparse_trtt_garbage_collect_batches (anv_sparse.c:525)

An alternative to these Valgrind macros would simply have been to
zero-intialize last_value.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31332>
2024-09-27 04:10:12 +00:00
Paulo Zanoni ab91106d4f anv: fix compute engines when using ANV_QUEUE_OVERRIDE
I just noticed that my custom sparse program was not working correctly
when I used ANV_QUEUE_OVERRIDE (instead of enabling the compute queue
by default or using INTEL_ENGINE_CLASS_COMPUTE, which was removed by
commit 600d88ab3c ("intel: Remove INTEL_ENGINE_CLASS_COMPUTE and
INTEL_ENGINE_CLASS_COPY parameters").

It turns out we were not setting the same engine class type when using
ANV_QUEUE_OVERRIDE vs the other cases. Move the code around so the
behavior can stay the same.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31332>
2024-09-27 04:10:12 +00:00
Matt Turner 75f02ed4b5 anv: Set shader_spilling_rate=15 by default
This avoids massively long shader compile times when there is lots of
spilling, at a minor cost of a few more spills/fills. Choose 15 as it is
already the default used by the Cyberpunk 2077 driconf workaround.

Surprisingly the number of additional spills/fills are miniscule in
fossil-db:

  Instructions in all programs: 152680595 -> 152681525 (+0.0%)
  SENDs in all programs: 7672789 -> 7672789 (+0.0%)
  Loops in all programs: 48469 -> 48469 (+0.0%)
  Cycles in all programs: 11981743456 -> 11984228708 (+0.0%)
  Spills in all programs: 42989 -> 42779 (-0.5%)
  Fills in all programs: 76380 -> 76776 (+0.5%)

partly because of the chaotic unpredictability that the choice of
registe to spill has on a shader. For example, this patch massively
helps some shaders in terms of spills/fills:

  Spills helped fossils/fossil-db/steam-native/red_dead_redemption2.vk-g6.foz/4101ff9c9b83bf22/SIMD8 fragment: 3208 -> 2894 (-9.8%)
  Fills helped fossils/fossil-db/steam-native/red_dead_redemption2.vk-g6.foz/4101ff9c9b83bf22/SIMD8 fragment: 7258 -> 6795 (-6.4%)
  Spills helped fossils/q2rtx/q2rtx-rt-pipeline.976f4ab1c0fee975.1.foz/c496e8a549f6b4bf/compute: 109 -> 92 (-15.6%)

Related: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31133
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9241
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11709
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11844
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31269>
2024-09-27 03:43:52 +00:00
Caio Oliveira 4e559077e4 intel/executor: Dump both pre-processed source and assembly
Having the actual generated assembly is helpful when trying to figure
out if the code emission and disassembly are implemented correctly.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31305>
2024-09-27 02:46:28 +00:00