b573b22628
panvk: Implement VK_KHR_synchronization2
...
It's easier to switch to sync2 before CmdPipelineBarrier gets any more
complicated.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15436 >
2022-03-18 08:15:50 +00:00
39c395d1d2
panvk: Move core properties into their respective core structs
...
Currently, we only support a few features from 1.1.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15436 >
2022-03-18 08:15:50 +00:00
ff30dd11a7
panvk: Re-arrange GetPhysicalDeviceProperties2
...
Put the 1.0 properties and limits first.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15436 >
2022-03-18 08:15:50 +00:00
34139d9f51
panvk: Add a 1.3 features struct
...
The only thing that gets pulled into this is private data.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15436 >
2022-03-18 08:15:50 +00:00
dd03dba7fd
panvk: Re-arrange GetPhysicalDeviceFeatures2
...
Put the 1.0 features at top followed by 1.1 and then 1.2. For filling
out the actual 1.1 and 1.2 structs, use the helpers.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15436 >
2022-03-18 08:15:50 +00:00
5c1302f47c
v3dv: expose VK_EXT_image_drm_format_modifier
...
This has been implemented for a while but we could not expose it on
Vulkan 1.0 because the extension declares a dependency on
VK_KHR_sampler_ycbcr_conversion, which we don't implement, and
CTS would complain.
On Vulkan 1.1 however, VK_KHR_sampler_ycbcr_conversion was promoted
to core as an optional feature, and this is enough for the the
dependency to be satisfied, even if the feature is not supported,
meaning that we can now expose the extension.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15426 >
2022-03-18 06:42:06 +00:00
cdd1b86591
lavapipe: add EXT_texel_buffer_alignment support.
...
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15442 >
2022-03-18 04:45:32 +00:00
efa724133f
zink: flag sample locations for re-set on batch flush
...
this needs to be re-set any time the cmdbuf changes
cc: mesa-stable
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15397 >
2022-03-18 04:31:49 +00:00
19330eeb1d
intel/fs: Force destination types on DP4A instructions
...
Most of the time, this doesn't matter. On the versions with _sat, if
the destination type is incorrect, the clamping will not happen
correctly.
Fixes the following CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_uu_v4i8_out32
v2: Update anv-tgl-fails.txt.
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Fixes: 0f809dbf40https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15417 >
2022-03-17 22:39:04 +00:00
3bd9b25060
intel: change INTEL_MEASURE output to microseconds
...
Change time event durations from ns -> us. Microseconds are easier
to work with.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
2e6d14cc7b
intel: increase INTEL_MEASURE batch/buffer sizes
...
Increase default batch_size and buffer_size from 16 -> 64. These
are sized to be big enough to service most games. As games have
become more demanding, larger sizes become necessary.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
e0c9032db8
anv: add indirect draw to INTEL_MEASURE
...
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
f452317849
clover/nir: respect lower to scalar options.
...
This just calls the lower alu to scalar pass like mesa/st
Reviewed-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15433 >
2022-03-17 22:00:49 +00:00
f34260bbf7
vulkan: update vk video headers for new vulkan headers.
...
These got out of sync update to the latest video headers.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15434 >
2022-03-17 21:14:28 +00:00
3d04c43576
tu: Trivially implement VK_EXT_texel_buffer_alignment
...
The previous alignment of 64 bytes, which we got from the blob,
indicates that single-texel alignment isn't supported. So just do a
trivial no-op implementation that returns the same alignment as before.
This matches what newer blobs that expose this extension do.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15427 >
2022-03-17 20:45:19 +00:00
177b54ebe9
aco/tests: add v_fma_mix tests
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
1092f37805
aco: use v_fma_mix to combine mul/add/fma output conversions
...
fossil-db (Sienna Cichlid):
Totals from 42 (0.03% of 134913) affected shaders:
CodeSize: 596904 -> 596332 (-0.10%); split: -0.10%, +0.00%
Instrs: 110194 -> 109902 (-0.26%)
Latency: 1205239 -> 1204915 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 189697 -> 189375 (-0.17%)
VClause: 1365 -> 1366 (+0.07%)
Copies: 5429 -> 5414 (-0.28%); split: -0.33%, +0.06%
Branches: 4034 -> 4026 (-0.20%)
fossil-db (Navi):
Totals from 42 (0.03% of 134913) affected shaders:
CodeSize: 596044 -> 595488 (-0.09%); split: -0.10%, +0.00%
Instrs: 110845 -> 110540 (-0.28%)
Latency: 1206131 -> 1205747 (-0.03%)
InvThroughput: 190178 -> 189809 (-0.19%)
VClause: 1372 -> 1370 (-0.15%); split: -0.29%, +0.15%
Copies: 5671 -> 5641 (-0.53%); split: -0.56%, +0.04%
Branches: 4033 -> 4025 (-0.20%)
fossil-db (Vega):
Totals from 42 (0.03% of 135048) affected shaders:
CodeSize: 605824 -> 605352 (-0.08%); split: -0.08%, +0.00%
Instrs: 115975 -> 115706 (-0.23%)
Latency: 1399845 -> 1398912 (-0.07%)
InvThroughput: 489901 -> 489442 (-0.09%)
VClause: 1314 -> 1311 (-0.23%); split: -0.38%, +0.15%
Copies: 9673 -> 9666 (-0.07%); split: -0.12%, +0.05%
Branches: 4025 -> 4024 (-0.02%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
21304b772c
aco: apply clamp to v_fma_mix
...
fossil-db (Sienna Cichlid):
Totals from 2536 (1.88% of 134913) affected shaders:
CodeSize: 17314568 -> 17282960pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
35196b6d89
aco: combine add/mul as v_fma_mix into fma
...
fossil-db (Sienna Cichlid):
Totals from 7345 (5.44% of 134913) affected shaders:
CodeSize: 73840060 -> 73768936 (-0.10%); split: -0.10%, +0.00%
Instrs: 13701603 -> 13684183 (-0.13%); split: -0.13%, +0.00%
Latency: 185389373 -> 185306538 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 33785020 -> 33757593 (-0.08%); split: -0.08%, +0.00%
VClause: 237337 -> 237338 (+0.00%)
SClause: 485728 -> 485720 (-0.00%)
Copies: 935900 -> 935279 (-0.07%); split: -0.07%, +0.00%
Branches: 480721 -> 480722 (+0.00%)
fossil-db (Navi):
Totals from 10649 (7.89% of 134913) affected shaders:
VGPRs: 756624 -> 756516 (-0.01%); split: -0.02%, +0.01%
CodeSize: 92156580 -> 91707900 (-0.49%); split: -0.49%, +0.00%
MaxWaves: 159402 -> 159476 (+0.05%); split: +0.07%, -0.02%
Instrs: 17155827 -> 17070449 (-0.50%); split: -0.50%, +0.00%
Latency: 246296456 -> 245487120 (-0.33%); split: -0.33%, +0.00%
InvThroughput: 41438159 -> 41117424 (-0.77%); split: -0.77%, +0.00%
VClause: 323790 -> 323867 (+0.02%); split: -0.00%, +0.03%
SClause: 612077 -> 612034 (-0.01%); split: -0.01%, +0.00%
Copies: 1103012 -> 1102775 (-0.02%); split: -0.03%, +0.01%
Branches: 555893 -> 555896 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 824372 -> 824378 (+0.00%)
PreVGPRs: 740390 -> 740363 (-0.00%); split: -0.01%, +0.01%
fossil-db (Vega):
Totals from 10950 (8.11% of 135048) affected shaders:
SGPRs: 1034528 -> 1034560 (+0.00%)
VGPRs: 794092 -> 794104 (+0.00%); split: -0.01%, +0.01%
CodeSize: 94409768 -> 93955568 (-0.48%); split: -0.48%, +0.00%
MaxWaves: 38950 -> 38939 (-0.03%); split: +0.00%, -0.03%
Instrs: 18162637 -> 18070934 (-0.50%); split: -0.51%, +0.00%
Latency: 291718455 -> 290772451 (-0.32%); split: -0.32%, +0.00%
InvThroughput: 109114674 -> 108489767 (-0.57%); split: -0.57%, +0.00%
VClause: 334498 -> 334579 (+0.02%); split: -0.01%, +0.03%
SClause: 628871 -> 628825 (-0.01%); split: -0.01%, +0.00%
Copies: 1674477 -> 1674850 (+0.02%); split: -0.02%, +0.04%
PreSGPRs: 834800 -> 834802 (+0.00%)
PreVGPRs: 750460 -> 750415 (-0.01%); split: -0.01%, +0.01%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
9934c86761
aco: use v_fma_mix to combine mul/add/fma input conversions
...
fossil-db (Sienna Cichlid):
Totals from 11558 (8.57% of 134913) affected shaders:
VGPRs: 829392 -> 825200 (-0.51%); split: -0.52%, +0.02%
SpillSGPRs: 7845 -> 8399 (+7.06%)
CodeSize: 101822704 -> 101677172 (-0.14%); split: -0.25%, +0.11%
MaxWaves: 172216 -> 173182 (+0.56%); split: +0.59%, -0.03%
Instrs: 19061343 -> 18883450 (-0.93%); split: -0.93%, +0.00%
Latency: 256011590 -> 255177378 (-0.33%); split: -0.39%, +0.06%
InvThroughput: 46104438 -> 45604059 (-1.09%); split: -1.12%, +0.04%
VClause: 352211 -> 351948 (-0.07%); split: -0.21%, +0.13%
SClause: 676506 -> 676961 (+0.07%); split: -0.04%, +0.11%
Copies: 1246571 -> 1237745 (-0.71%); split: -0.97%, +0.26%
Branches: 626229 -> 626241 (+0.00%); split: -0.02%, +0.03%
PreSGPRs: 882176 -> 888853 (+0.76%); split: -0.00%, +0.76%
PreVGPRs: 796705 -> 792304 (-0.55%); split: -0.56%, +0.00%
fossil-db (Navi):
Totals from 11558 (8.57% of 134913) affected shaders:
VGPRs: 803900 -> 798660 (-0.65%); split: -0.73%, +0.08%
SpillSGPRs: 7894 -> 8492 (+7.58%); split: -0.10%, +7.68%
CodeSize: 96892596 -> 97134716 (+0.25%); split: -0.05%, +0.29%
MaxWaves: 181454 -> 183014 (+0.86%); split: +0.94%, -0.08%
Instrs: 18186813 -> 18093994 (-0.51%); split: -0.56%, +0.05%
Latency: 253385909 -> 253325528 (-0.02%); split: -0.15%, +0.12%
InvThroughput: 43315355 -> 42805541 (-1.18%); split: -1.33%, +0.15%
VClause: 338755 -> 338535 (-0.06%); split: -0.16%, +0.10%
SClause: 656561 -> 656829 (+0.04%); split: -0.07%, +0.11%
Copies: 1162235 -> 1153558 (-0.75%); split: -1.07%, +0.32%
Branches: 588536 -> 588542 (+0.00%); split: -0.03%, +0.03%
PreSGPRs: 854849 -> 861640 (+0.79%); split: -0.00%, +0.80%
PreVGPRs: 783401 -> 779031 (-0.56%); split: -0.56%, +0.00%
fossil-db (Vega):
Totals from 11516 (8.53% of 135048) affected shaders:
SGPRs: 1072128 -> 1076288 (+0.39%); split: -0.01%, +0.40%
VGPRs: 821312 -> 818124 (-0.39%); split: -0.43%, +0.04%
SpillSGPRs: 11952 -> 12677 (+6.07%)
CodeSize: 96378496 -> 96707596 (+0.34%); split: -0.04%, +0.38%
MaxWaves: 42614 -> 42883 (+0.63%); split: +0.68%, -0.04%
Instrs: 18672844 -> 18600274 (-0.39%); split: -0.44%, +0.05%
Latency: 296658786 -> 296338296 (-0.11%); split: -0.21%, +0.10%
InvThroughput: 111665547 -> 111283559 (-0.34%); split: -0.40%, +0.06%
VClause: 343001 -> 342826 (-0.05%); split: -0.14%, +0.09%
SClause: 646684 -> 646657 (-0.00%); split: -0.05%, +0.04%
Copies: 1715316 -> 1712895 (-0.14%); split: -0.53%, +0.39%
PreSGPRs: 850737 -> 856543 (+0.68%); split: -0.04%, +0.72%
PreVGPRs: 775293 -> 772215 (-0.40%); split: -0.41%, +0.02%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
eeef1bbe65
aco: refactor selection of mad/fma
...
In the future, whether we need to use fma will depend on which
multiplication is chosen.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
e12bee3cb7
aco: improve support for v_fma_mix
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
79c8740c6e
aco: fix fp16 opcode definitions
...
The v_fma_mix optimizations assume v_cvt_f16_f32 and v_mul_f16 use a v2b
definition.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769 >
2022-03-17 19:04:17 +00:00
6d4eb4a72e
mesa/main: replace use of simple_list with util/list
...
Because really, do we want simple_list?
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14983 >
2022-03-17 18:25:55 +00:00
4b10a4aaaa
util/list.h: Add docstrings for list_add and list_addtail
...
Which have easily confused parameters: the first argument is the item to
be added, the second is the list to add to; but this could easily be the
other way around.
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14983 >
2022-03-17 18:25:55 +00:00
b0faf422b7
pan/va: Use XML for special FAU page 0
...
Now all special FAU handling is unified, which makes both assembler and
disassembler considerably nicer. This adds some more special FAU indices from
page 0 that were previously missing, allowing them to be assembled and
disasembled.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
31a171d92d
pan/va: Use boring names for FAU special pages 1/3
...
There's no magic underlying interpretation, be.. uniform.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
76159ee379
pan/va: Remove immediate modes from XML/asm
...
Now replaced by inference in the assembler, as they should be.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
81498f1538
pan/va: Use 64-bit special FAU for pages 1 and 3
...
This aligns with how the hardware actually sees special FAU.
Also fix the names while we're at it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
139867cb43
pan/va: Rename imm_mode -> fau_page
...
In accordance with new information on the hardware.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
3bd1401075
pan/va: Handle uniforms from page 1
...
Like Bifrost, Valhall can access 2x as many fast acess uniforms as previously
thought. However, on Valhall this requires using the pagination mechanism.
Support this in the dis/assembler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
cf43a1cc58
pan/va: Rewrite FAU handling in dis/assembler
...
FAU pages do not need to be specified explicitly in the assembly. Rather, they
should be inferred by the assembler by the instructions used. Rewrite the code
handling this in alignment with new information about the hardware.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
95b7908d2d
pan/va: Fix BLEND instruction
...
There's only one staging register, the other register is just offset due to the
Msg64 source.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
c7e8e8b319
pan/va: Handle 64-bit sources in message instrs
...
These take up two slots, reading an aligned register pair, even though they are
in a 32-bit instruction. Required to correctly model BLEND.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
9878469833
pan/va: Add start property to source
...
The bit position of sources is more complicated than (8 * index). Make it a part
of the Valhall reflection information.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
5a759140b0
pan/va: Fix typo in BLEND text
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364 >
2022-03-17 18:06:17 +00:00
96e17287b4
ci/freedreno: Disable a618 jobs
...
Some of these machines are experiencing networking problems currently.
Disable for now so people aren't blocked.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15430 >
2022-03-17 17:43:06 +00:00
115298b71e
gallium: rename ballot cap
...
This cap is no longer TGSI specific, so let's rename it to reflect
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
b3ce733da9
gallium: rename clock cap
...
This cap is no longer TGSI specific, so let's rename it to reflect
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
7984c5884c
gallium: rename group-vote cap
...
This cap is no longer TGSI specific, so let's rename it to reflect
reality.
Because the name got a bit vague when removing the TGSI-bits, let's add
some more details to the name.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
a6d7ead686
gallium: rename texture query samples cap
...
This isn't specific to TGSI, so let's update the name to reflect
reality.
Because the name of the opcode was TGSI specific, let's pick a new one,
based on the naming of the PIPE_CAP_TEXTURE_QUERY_LOD cap.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
930b38e7cd
gallium: rename read-outputs cap
...
This cap is no longer TGSI-specific, so let's update the name to reflect
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
2dff9bea4f
gallium: rename array-components cap
...
This cap is no longer TGSI specific, so let's update the name to reflect
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
350329feb1
gallium: rename sysval caps
...
These aren't spiecic to TGSI any more, so let's rename them to reflect
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
df40de91d9
gallium: rename fine derivative cap
...
This is no longer TGSI specific, so let's rename it to reflect the
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
2a8e11e101
gallium: rename pixel-coord caps
...
These aren't specific to TGSI, so let's rename them to reflect the
reality.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:42 +00:00
89797fac56
gallium: rename layer-viewport caps
...
Similar to the previous commits, these aren't TGSI specific, so let's
drop TGSI from their name.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:41 +00:00
8ac7dc9cf6
gallium: rename vs instance id cap
...
This cap is no longer specific to TGSI, so let's rename it and update
the documentation to reflect that.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:41 +00:00
f8809fbdb8
gallium: rename pack half-float cap
...
This cap no longer has anything to do with TGSI, as the lowering happens
on GLSL IR, and applies just as much to NIR drivers. So let's rename
this cap and update the docs to reflect the current situation.
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: Ian Romanick <ian.d.romanick@intel.com >
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316 >
2022-03-17 16:44:41 +00:00
0f048c5782
panvk: Convert to the common sync/submit framework
...
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15296 >
2022-03-17 16:22:10 +00:00
Jason Ekstrand