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aco: fix fp16 opcode definitions

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The v_fma_mix optimizations assume v_cvt_f16_f32 and v_mul_f16 use a v2b
definition.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769>
This commit is contained in:
Rhys Perry
2022-02-23 11:33:16 +00:00
committed by Marge Bot
parent 6d4eb4a72e
commit 79c8740c6e
1 changed files with 4 additions and 3 deletions
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src/amd/compiler/aco_instruction_selection.cpp
+4 -3
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@@ -2520,7 +2520,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
aco_ptr<Instruction> norm;
if (dst.regClass() == v2b) {
Temp half_pi = bld.copy(bld.def(s1), Operand::c32(0x3118u));
Temp tmp = bld.vop2(aco_opcode::v_mul_f16, bld.def(v1), half_pi, src);
Temp tmp = bld.vop2(aco_opcode::v_mul_f16, bld.def(v2b), half_pi, src);
aco_opcode opcode =
instr->op == nir_op_fsin ? aco_opcode::v_sin_f16 : aco_opcode::v_cos_f16;
bld.vop1(opcode, Definition(dst), tmp);
@@ -3334,7 +3334,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
}
case nir_op_fquantize2f16: {
Temp src = get_alu_src(ctx, instr->src[0]);
Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v2b), src);
Temp f32, cmp_res;
if (ctx->program->chip_class >= GFX8) {
@@ -7642,7 +7642,8 @@ emit_addition_uniform_reduce(isel_context* ctx, nir_op op, Definition dst, nir_s
if (op == nir_op_fadd) {
src_tmp = as_vgpr(ctx, src_tmp);
Temp tmp = dst.regClass() == s1 ? bld.tmp(src_tmp.regClass()) : dst.getTemp();
Temp tmp = dst.regClass() == s1 ? bld.tmp(RegClass::get(RegType::vgpr, src.ssa->bit_size / 8))
: dst.getTemp();
if (src.ssa->bit_size == 16) {
count = bld.vop1(aco_opcode::v_cvt_f16_u16, bld.def(v2b), count);