AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
112,493 Commits 1 Branch 0 Tags
af29ad7cc6b122bfdfd15ae4b67951c9c679a022
Commit Graph

103783 Commits

Author SHA1 Message Date
Nicolai Hähnle af29ad7cc6 radeonsi/gfx10: set MAX_ALLOC_COUNT 
The number for Vega was copied from PAL and has no effect because of MIN2.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 594010e366 radeonsi/gfx10: require LLVM 9 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang de99e0a563 radeon/vcn: update for new vcn enc interface 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 9ab1e427bb radeonsi: enable jpeg decode for navi10 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 6480c7b577 radeon/vcn: implement vcn 2.0 jpeg decode 
Use direct register to implement vcn 2.0 jpeg deocde

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 0cd7953ece radeon/vcn: add direct register bool 
VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 7a5c22d32a radeon/vcn: add defines for vcn 2.0 jpeg 
Add neccesary register defines for vcn 2.0 jpeg deocde

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 0c27971157 radeon/vcn: use variable to assign ib cmd 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 587b9c5dae radeon/vcn: implement vcn 2.0 encode 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 40e1bed389 radeon/vcn: add vcn2.0 encode skeleton 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
(v2: build fix -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 8f6272d494 radeon/vcn: move vcn1.0 specific defines to c 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang b5287a9fa6 radeon/vcn: assign function pointer with ib functions 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang 9940a6e066 radeon/vcn: add function pointer for ib functions 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang c6b5188505 radeon/vcn: move header related algorithm to vcn_enc 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang dd46740bc2 radeon/vcn: move add buf func to common file 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Boyuan Zhang e6ca4d1bd8 radeon/vcn: move cs defines to enc header file 
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu 874881b26b radeon/vcn: add VP9 support for Navi10 
It requires bigger DPB and context buffers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu 9bbb546c4f radeonsi: enable encode support for newer HW 
Previously it was Raven only allowed to do so

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu d6acd29c9a radeon/vcn: add VCN2 set of internal registers for IB 
From VCN2.0, the RBC have different views on the registers

Signed-off-by: Leo Liu <leo.liu@amd.com>
(v2: rebase -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Leo Liu a38268ea5b radeonsi/uvd: allow newer HW to create HW decoder 
Previously it was Raven only allowed to do so

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 84e7ee421f ac/surface/gfx10: allow "rotated" micro mode 
Standard mode does not support DCC.

The R is retconned to "render target" on gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle a66be784c3 ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modes 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 97ddcfff7c amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not support 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 9eb4a79345 amd/addrlib/gfx10: fix assertion in Addr2IsValidDisplaySwizzleMode 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 6d416ac7e1 amd/common/gfx10: print gfx10 registers in debug dumps 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 70fd27d1e3 amd/common/gfx10: CMASK is only used for FMASK 
All regular color compression is done via DCC.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle b52bf8f12a amd/common/gfx10: support new tbuffer encoding 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle c067aaa580 amd/common/gfx10: pad shader buffers for instruction prefetch 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 227c29a80d amd/common/gfx10: implement scan & reduce operations 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 7ba80c1d19 amd/common/gfx10: add GS_ALLOC_REQ message define 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 4c364c89e2 amd/common/gfx10: print out GCR_CNTL as part of {ACQUIRE,RELEASE}_MEM 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 74a26af913 amd/common/gfx10: add register JSON 
A small number of fields now need new disambiguation.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 536782b0b7 amd/common: add GFX10 chips 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle db7e7a6cb5 radv: gfx10 is not supported 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Marek Olšák 78cdf9a99f amd/addrlib: add gfx10 support 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 112bf7f900 radeonsi: make emit_streamout_output externally accessible 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle e241b405ca radeonsi: pass the context to query destroy functions 
We'll need this in the future.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 064f195ef0 radeonsi: make si_restore_qbo_state externally available 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 04e27ec136 radeonsi: make get_primitive_id externally visible 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 5059a4df8a radeonsi: make si_llvm_export_vs externally available 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Nicolai Hähnle 4a774ba893 radeonsi: various si_translate_*format functions only apply to pre-gfx10 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Marek Olšák c53e6ea05d radeonsi: use a fragment shader blit instead of DB->CB copy for ZS CPU mappings 
This mainly removes and simplifies code that is no longer needed.

There were some issues with the DB->CB stencil copy on gfx10, so let's
just use a fragment shader blit for all ZS mappings. It's more reliable.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2019-07-03 15:51:12 -04:00
Marek Olšák 6686d8a130 gallium/u_blitter: implement copying from ZS to color and vice versa 
This is for drivers that can't map depth and stencil and need to blit
them to a color texture for CPU access.

This also useful for drivers using separate depth and stencil.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2019-07-03 15:51:12 -04:00
Marek Olšák 13a5e9d685 gallium/util: rewrite depth-stencil blit shaders 
- merge all 3 functions (Z, S, ZS)
- don't write the color output
- read the value from texel.x, then write it to position.z or stencil.y
  (don't use the value from texel.y or texel.z)

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2019-07-03 15:51:12 -04:00
Marek Olšák 131d40cfc9 st/mesa: accelerate glCopyPixels(STENCIL) 
Tested-by: Dieter Nützel
 2019-07-03 15:50:04 -04:00
Yevhenii Kolesnikov 65dc4db08e glsl/standalone: meson test for --dump-builder 
Added meson test for standalone compiler with --dump-builder option
on builtin texture* functions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107767
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
 2019-07-03 12:13:37 -07:00
Sergii Romantsov 9f85b4940c glsl/standalone: exit on unsupported texture functions 
glsl/standalone with --dump-builder will exit when unsupported texture
functions are encountered.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107767
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
 2019-07-03 12:13:37 -07:00
Pierre-Eric Pelloux-Prayer ea5b7de138 radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled 
gl_SampleMaskIn is 1 when R_028BE0_PA_SC_AA_CONFIG is 0, so this commit rework the conditions
controlling this register.

Before it was set if the sctx->framebuffer had a sample count > 1.

Now we still require this condition, but we also need either:
  - GL_MULTISAMPLE to be enabled
  - to be executing an operation that doesn't depends on GL state using u_blitter.

This fixes the arb_sample_shading/sample_mask piglit tests on radeonsi.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2019-07-03 14:59:21 -04:00
Brian Paul 7bb3d6acec gallium/u_blitter: enable MSAA when blitting to MSAA surfaces 
If we're doing a Z -> Z MSAA blit (for example) we need to enable
msaa rasterization when drawing the quads so that we can properly
write the per-sample values.

This fixes a number of Piglit ext_framebuffer_multisample blit tests
such as ext_framebuffer_multisample/no-color 2 depth combined with
the VMware driver.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2019-07-03 14:59:15 -04:00
Alexandros Frantzis e5be4351c2 virgl: Clear the valid buffer range when possible 
If we are discarding the whole resource, we don't care about previous contents,
and the resource storage is now unused, either because we have created new
resource storage, or because we have waited for the existing resource storage
to become unused, or because the transfer is unsynchronized.

In the last two cases this commit marks the storage as uninitialized, but only
if the resource is not host writable (in which case we can't clear the valid
range, since that would result in missed readbacks in future transfers).

In the first case, when the whole resource discard involves a reallocation, the
reallocation and subsequent rebinding already update the valid buffer range
appropriately.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
 2019-07-03 09:59:55 -07:00