ad459054ed
radv: enable SQTT tracing on GFX11
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20338 >
2023-02-21 07:28:49 +00:00
dfa9b5d624
radv: disable SPM counters with RGP on GFX11
...
They are likely different and perfcounters aren't defined on GFX11 yet.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20338 >
2023-02-21 07:28:49 +00:00
5fe48baad6
radv: implement a workaround for SQTT on GFX11
...
Found in AMDVLK, see the comment below for an explanation.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20338 >
2023-02-21 07:28:49 +00:00
826ae89ba6
radv: make sure to wait for the trace buffer also on GFX11
...
Otherwise, we might get incomplete data.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20338 >
2023-02-21 07:28:49 +00:00
c2bc4aff54
radv: only enable SQTT for SE0 on GFX11
...
For weird reasons, the hardware doesn't return any data for other SEs.
RadeonSI is also affected by the same issue, enable only SE0 for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20338 >
2023-02-21 07:28:49 +00:00
ad4ad2ba84
radv: configure SQ_THREAD_TRACE_CTRL.REG_AT_HWM on GFX11
...
AMDVLK sets this to 2 when the always stall mode is enabled, which is
the default in RADV.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20338 >
2023-02-21 07:28:49 +00:00
8bc78e8eb9
util/u_process: implement util_get_command_line for BSDs
...
Acked-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21052 >
2023-02-20 21:26:49 +00:00
923758a5c2
winsys/amdgpu: use amdgpu_device_get_fd
...
If radv is initialized before radeonsi, doing:
aws->fd = fd;
is incorrect because the device was initialized using the fd
passed by radv.
libdrm has a helper to query the fd used to create the device,
so use it.
We also need to init the kms_handles table in this case
because we're going to share BOs between radeonsi's fd and
the device fd.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3424
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20983 >
2023-02-20 20:38:17 +00:00
919c5568bf
freedreno: check for conditional rendering in launch_grid
...
fixes: KHR-GL45.compute_shader.conditional-dispatching
Signed-off-by: Amber Amber <amber@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21428 >
2023-02-20 19:03:25 +00:00
e93a221024
agx: Handle group_memory_barrier
...
A combination of control_barrier + memory_barrier but it's always seen with
those. This would be safer with scoped barriers...
Fixes dEQP-GLES31.functional.synchronization.inter_invocation.ssbo
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:40 +00:00
e9cec96633
agx: Implement b2b32
...
Shows up with store_shared.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:40 +00:00
955797bb00
agx: Pack local atomics
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
14f546726e
agx: Lower shared memory offsets to 16-bit
...
Per the hardware requirement. This simplifies instruction selection (it avoids
the need to constant fold u2u16 in the backend).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
a21f6f8cb0
agx: Translate load/store_shared
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
f8b9dfbbad
agx: Translate NIR atomics
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
2a021b1818
agx: Pack local load/store instructions
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
96904f83b4
agx: Pack global atomics
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
eea3674f36
agx: Disallow immediate bases to device_load
...
Lina pointed this out in review.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
6b0ef2b462
agx: Model local loads/stores
...
Aka shared memory or threadgroup memory.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
0d07d27173
agx: Model atomic instructions
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21326 >
2023-02-20 18:50:39 +00:00
ec7584130f
iris: Export num_fences()
...
This function will be needed by i915 and Xe backends.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21389 >
2023-02-20 18:29:47 +00:00
780dd291c5
iris: Export update_batch_syncobjs()
...
This function will be needed by i915 and Xe backends.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21389 >
2023-02-20 18:29:47 +00:00
102e180d0f
iris: Export batch debug functions
...
Those function will be called by different backends, so exporting it.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21389 >
2023-02-20 18:29:47 +00:00
9e67d3f237
asahi: Advertise ARB_texture_barrier
...
We already implement it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21264 >
2023-02-20 17:27:21 +00:00
5f8a59ac89
asahi: Advertise ARB_derivative_control
...
Our native fddx instruction is already fine, so it's fine to use it for both
fddx_coarse and fddx_fine. We handle both of those cases already so the
extension is trivial.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21264 >
2023-02-20 17:27:21 +00:00
c6c61d052e
docs/features: Sync Asahi with reality
...
A few features were either missed in the original patch or have since been
added, update features.txt to light up more green on the mesa matrix.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21264 >
2023-02-20 17:27:21 +00:00
cf96edff1c
agx: Implement gathers (nir_texop_tg4)
...
Passes dEQP-GLES31.functional.texture.gather.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21264 >
2023-02-20 17:27:21 +00:00
978d3fefa8
agx: Model and pack gathers
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21264 >
2023-02-20 17:27:21 +00:00
8dc861dbb5
agx: Lower offsets in NIR
...
Rather than the backend. This way we can handle non-constant offsets as well as
constants with a single code path (with the constant offset code subsumed as a
special case via NIR's constant folding). This nets us dynamic offset support.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21264 >
2023-02-20 17:27:21 +00:00
a5dfee1c22
ci: revert download of git cache to the wget
...
At this point of CI there is not curl available.
Fixes: 796686af1bdavid.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21414 >
2023-02-20 13:48:32 +00:00
44f40ff941
pvr: Use descriptor/set/table offsets from driver
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Co-Authored-By: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:03 +00:00
e64288a0ba
pvr: Split pvr_private.h
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:03 +00:00
5694755fa0
pvr: Load descriptors from memory
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:03 +00:00
3355749105
pvr: Support loading immediate values
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:03 +00:00
e0e58e9659
pvr: Additional register subarray support
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:03 +00:00
888e06b8cc
pvr: Add bitwise instruction support
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
93fa2f6265
pvr: Add memory load support
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
81f86a559c
pvr: Add ADD64 support
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by Frank Binns <frank.binns@imgtec.comr >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
7386342a19
pvr: Add PVR_SELECT() helper macro
...
For pvr_setup_descriptor_mappings_new() there will be quite a few
variables of which the value depend on the stage so rather than
having all that selection in the `switch` at the beginning of the
function the helper macro provides a compact selection in the
desired scope.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
ce67f5ac94
pvr: Write descriptor set addrs table dev addr into shareds
...
Previously UBOs and various buffers, as well as the native
descriptor sets were DMAed into the shared registers. This added
complexity in allocating the registers and various other places.
We also ended up being in situations were we wouldn't know the size
of a buffer by the time the shaders were being compiled. It would
be possible to determine the size by inspecting the shader but
that would introduce more complexity in the compiler.
To get things working sooner, avoid extra complexity for
now, a different approach was devised.
The driver will write the addresses of the currently bound
descriptor sets into a device buffer. The device buffer is referred
to as the descriptor set addrs table. The dev addr of the table is
written into a shared register. To access the buffers the shader
will first get the address of the descriptor set from the in memory
table. Then get the primary descriptor from the descriptor set. And
finally access the in memory buffer with the address it read from
the descriptor. Essentially there's three level of indirection and
all the buffers are in memory. The shader will know what offset the
primary descriptor is located based on the descriptor set layout.
The descriptor set address could have been written into the shareds
directly but that would require extra handling on the compiler side
so opted to just write the table address instead.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
d67ed3eb24
pvr: Change last_DMA to last_dma
...
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
5405277b38
pvr: Put old descriptor set approach behind a hardcoding check
...
This commit sets up the infrastructure to introduce the new
descriptor set approach while keeping the old paths so the
hard coded apps are still operational. The old paths will be
removed once the compiler can compiler shaders for those apps
and the driver-compiler interface is fully flushed out.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
b7f8a120bf
pvr: Store enum pvr_stage_allocation instead of VkShaderStageFlags
...
This commit changes the pipeline layout, desc. set layout,
and desc. set layout binding to keep track of shader stage usage
with a mask of enum pvr_stage_allocation instead of
VkShaderStageFlags.
This commit also makes renames the relevant fields to
'shader_stage_mask' to make the naming uniform across stucts.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com >
Reviewed-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21331 >
2023-02-20 13:34:02 +00:00
15f1478eb9
radv/ci: move CI lists for external GPUs in separate folder
...
A bunch of CI lists are maintained by ourselves with GPUs outside of
Mesa CI. Move them to a separate folder to avoid confusion.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21417 >
2023-02-20 13:05:50 +00:00
f334704078
radv/ci: disable vkcts-kabini-valve
...
It's no longer reachable.
Suggested-by: Martin Roukala <martin.roukala@mupuf.org >
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21417 >
2023-02-20 13:05:50 +00:00
dee4784e53
asahi: Fix rendering into mipmapped framebuffers
...
batch->key.width will be minified, but then the PBE::level field will
incorrectly minify again.
Fixes dEQP-GLES31.functional.shaders.framebuffer_fetch.basic.framebuffer_texture_level
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21400 >
2023-02-20 11:47:56 +00:00
0e0825013d
agx: Do more work in agx_preprocess_nir
...
agx_preprocess_nir runs once per shader, whereas agx_optimize_nir runs once per
variant. That means we want to do as much work as possible in agx_preprocess_nir
to make shader variants as cheap as possible to compiler. So, move our standard
suite of lowering and optimizing to the preprocess loop, leaving just a single
(easy) trip through the optimizer for simple variant processing.
Plus, we can remove variables when preprocessing, since we no longer use
variables anywhere. We remove them to reduce the RAM and disk cache footprint of
shader variants.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21104 >
2023-02-20 11:34:58 +00:00
5b92bd99db
agx: Don't treat clip distances specially
...
We've been using the clip lowering, but it's been broken upstream because of
this artefact from the (non-lowered implementation) sneaking in from downstream.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21104 >
2023-02-20 11:34:58 +00:00
99a6afd1a6
asahi: Only apply FS lowerings to fragment shaders
...
Signed-off-by: Asahi Lina <lina@asahilina.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21104 >
2023-02-20 11:34:58 +00:00
2adea481f1
asahi: Move agx_preprocess_nir to CSO create
...
Now we preprocess shaders once at link time, rather than every time we spawn a
variant. This should reduce variant pain.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21104 >
2023-02-20 11:34:58 +00:00
Samuel Pitoiset