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Author SHA1 Message Date
Peyton Lee
17c20ceda7 amd,radeonsi: add libvpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Alan Liu <haoping.liu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
6b441ef6ab frontends, va: add new parameters of post processor 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Jesse Natalie
be05c9458a microsoft/clc: Fix image lowering pass to only erase variables at the end 
Otherwise, if a variable has multiple derefs in a shader, we'll crash
trying to remove it a second time. No idea how that can happen though,
seems derefs got sunk by opt_dead_cf.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26435>
 2023-11-30 23:32:08 +00:00
Lynne
aff59c63eb radv: change queue family order in radv_get_physical_device_queue_family_properties 
Fixes: 748b7f80ef ("radv: Move sparse binding into a dedicated queue.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26428>
 2023-11-30 22:45:49 +00:00
José Roberto de Souza
42dd48e933 anv: Fix vm bind of DRM_XE_VM_BIND_FLAG_NULL 
In this case bo is NULL so application was crashing when it was trying
to get the alloc_flags of bo to get the intel_device_info_pat_entry.

Fixes: 1a0d3504d5 ("anv: Fill PAT fields in Xe KMD gem_create and vm_bind uAPIs")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26430>
 2023-11-30 22:22:41 +00:00
Rhys Perry
5bc27e80c9 ac/nir: fix 32-bit offset global access optimization 
Since 38cff03e58 ("radv: use nir_lower_conv64"), u2u64(a) is replaced
with pack_64_2x32_split(a, 0).

fossil-db (navi31):
Totals from 1203 (1.52% of 79330) affected shaders:
MaxWaves: 33685 -> 33813 (+0.38%)
Instrs: 1407031 -> 1374689 (-2.30%); split: -2.32%, +0.02%
CodeSize: 7088652 -> 6917320 (-2.42%); split: -2.43%, +0.01%
VGPRs: 69276 -> 68988 (-0.42%); split: -0.43%, +0.02%
SpillSGPRs: 982 -> 977 (-0.51%); split: -0.92%, +0.41%
Latency: 12536511 -> 12451605 (-0.68%); split: -0.94%, +0.27%
InvThroughput: 2456803 -> 2431241 (-1.04%); split: -1.09%, +0.05%
VClause: 27624 -> 27832 (+0.75%); split: -1.88%, +2.64%
SClause: 31757 -> 32702 (+2.98%); split: -0.53%, +3.51%
Copies: 90923 -> 91238 (+0.35%); split: -1.47%, +1.81%
Branches: 25127 -> 25128 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 46025 -> 46068 (+0.09%); split: -0.53%, +0.62%
PreVGPRs: 53944 -> 53488 (-0.85%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Rhys Perry
10ba06960f ac/nir: ignore 8/16-bit global access offset 
This was found by inspection, I'm not sure it can even happen.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Caio Oliveira
bbb12dbbf9 intel/compiler: Add a few tests to opt_predicated_break 
v2 (idr): Fix expectations BottomBreakWithContinue. opt_predicated_break
will remove the IF and make the CONTINUE predicated.

v3 (idr): Temporarily disable the one test that fails.

v4 (idr): Free strings allocated by open_memstream. Fixes gitlab CI
failures in debian-testing-asan.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Caio Oliveira
0b072c5351 intel/compiler: Sort lists of succs and preds in CFG dump output 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Caio Oliveira
47c5656f0e intel/compiler: Allow dumping CFG to a specific FILE* 
Add optional argument for both cfg and block dump() function to pass
a FILE*.  Default behavior remains dumping to stderr.

v2 (idr): Don't add the new test framework in this commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Caio Oliveira
21cf9323f0 intel/compiler: Add a few more helpers to fs_builder 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
c0ecc0d70b intel/compiler: Don't promote CFG link types when removing a block 
Imagine 3 blocks A, B, and C. A has a physical link to B, and B has a
logical link to C. Previous to this commit, if B were removed, A would
get a logical link to C. This is not correct.

This was specifically observed to occur when block A was a DO block and
B was the WHILE block. The DO block would have two logical successors,
and that is completely invalid.

v2: Assert that the links from A-to-B and B-back-to-A are the same
kind. Suggested by Caio.

v3: Assume the successor and predecessor lists are well formed. Use this
to simplify the logic. Suggested by Caio. Add checks to cfg_t::validate
to ensure the lists are well formed.

v4: Remove (now unused) bblock_link_invalid. Suggested by Curro.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
77c0c1ce54 intel/compiler: Don't create extra CFG links when deleting a block 
The previous is_successor_of and is_predecessor_of checks prevented
creating a physical link when a logical link already existed. However, a
logical link could be added when a physical link already existed. This
change causes an existing physical link to be "promoted" to a logical
link.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
7e842a75ac intel/compiler: Don't create extra CFG links in opt_predicated_break 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
bbd7729993 intel/compiler: Delete bidirectional block links in opt_predicated_break 
Previously when earlier_block->children.make_empty() was called, the
child blocks would still have links back to earlier_block.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
5842829380 intel/compiler: Limit scope of cur_endif variable 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
02f9bbf6f3 intel/compiler: Add basic CFG validation 
v2: Use _mesa_shader_stage_to_abbrev(stage) instead of
stage_abbrev. Noticed by Caio and GCC. That's what I get for not
recompiling after rebasing. Wrap cfg_t::validate in NDEBUG
magic. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
19db6f1cd9 intel/vec4: Don't emit an empty ELSE 
This matches the behavior of fs_visitor::nir_emit_if.

This is not technically wrong, but the cfg_t generates some invalid
parent / child links in this case.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Rohan Garg
f3d99e3535 anv: introduce ANV_TIMESTAMP_REWRITE_INDIRECT_DISPATCH 
In order to rewrite timestamps for indirect dispatch's, instroduce a
ANV_TIMESTAMP_REWRITE_INDIRECT_DISPATCH that repacks the PostSync field
for a EXECUTE_INDIRECT_DISPATCH.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
9dd49e7a63 anv: memcpy the thread dimentions only when they're on the CPU 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
d161e3c2e2 iris: Emit a EXECUTE_INDIRECT_DISPATCH when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DISPATCH that allows us to:

  * Skip issuing mi load/store instructions for indirect parameters

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
580728564e anv: Emit a EXECUTE_INDIRECT_DISPATCH when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DISPATCH that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
6d4f43f0d6 anv: Emit EXECUTE_INDIRECT_DRAW when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DRAW that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters
  * Skip doing the indirect draw unroll on the CPU side when the
    appropriate stride is passed

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
7a9e82e82f genxml/12.5: Add the EXECUTE_INDIRECT_DISPATCH instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
4229757309 genxml/12.5: Add the EXECUTE_INDIRECT_DRAW instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg
6e060d99ba intel/dev: Add a bit for when the HW can do a indirect draw/dispatch unroll 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg
fa350862e9 anv: refactor kernel dispatch to use new common functions 
Refactor the function to use the new common functions introduced for
indirect dispatch previously.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg
51d2d9a665 anv: Refactor loading indirect parameters and filling IDD 
Refactor out loading the indirect parameters and filling the interface
descriptor data.

Reworks:
 * Jordan: Change anv to use get_interface_descriptor_data which
   returns the IDD struct rather than filling it.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Gert Wollny
ac4b8aab21 r600/sfn: Fix usage of std::string constructor 
Fixes: f718ac6268 (r600/sfn: Add a basic nir shader backend)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26415>
 2023-11-30 16:42:43 +00:00
Gert Wollny
eb25c7a4e2 r600/sfn: keep workgroup and invocation ID registers for whole shader 
For some reason one must not overwrite these values "too early", so
pin them for the whole shader.

Fixes: 79ca45 (r600/sfn: rewrite NIR backend)
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10004

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25846>
 2023-11-30 16:04:05 +00:00
Gert Wollny
5de814171b r600/sfn: Allow skipping backend shader optimization for a subset of shaders 
This comes in handy when debugging problems with the backend optimizer

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25846>
 2023-11-30 16:04:05 +00:00
Erik Faye-Lund
777c25255b panfrost: minify dimensions when converting modifiers 
When blitting resources, we need to specify the boxes in mip-level sized
coordinates. For the X and Y coordinates, missing this makes things
behave correctly, but only because we end up clipping away the excess
area.

However, for the Z coordinate of 3D textures, this will make us read
outside of the mip-chain during blitting, making us stumble and crash.

But let's fix what we do for all dimensions. And while we're at it,
rewrite the code a bit, so we don't end up computing any needless
values.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26077>
 2023-11-30 15:43:59 +00:00
José Roberto de Souza
b27ca68143 intel/dev: Adjust prefetch_size values for Xe2 engines 
Xe2 follows MTL and has different prefetch sizes for different
types of engines.

BSpec: 60223
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26396>
 2023-11-30 14:54:04 +00:00
Boyuan Zhang
046cc51223 radeonsi/vcn: add new logic for hevc multi slices reflist 
For multi slices hevc decoding, use the newly defined buffer to handle
the case for multi slices ref pic list.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:34 -05:00
Boyuan Zhang
d07517d19f radeonsi: add new interface to handle multi slice reflist 
Add new flag and buffer to handle multi slice reflist case for hevc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:31 -05:00
Boyuan Zhang
ffdc83e9dd frontend/va: add support for multi slices reflist 
According to codec spec, hevc supports different reference picture lists
for multi slices case. For example, each slice can have it's own ref pic
list. Add this support to pipe, and modify both frontend/va and radeonsi
accordingly.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:28 -05:00
Boyuan Zhang
26237b9807 gallium/pipe: define hevc max slices number 
No logic change, just use define instead of hardcoded number to make
it more clear.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26081>
 2023-11-30 08:39:25 -05:00
Eric Engestrom
02fe92c908 ci: disable opengl & gles in debian-vulkan build 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26369>
 2023-11-30 08:47:07 +00:00
Eric Engestrom
69ec13b303 bin/python-venv: detect python version change 
The venv only works for a specific python version; when updating python,
the venv needs to be regenerated.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26354>
 2023-11-30 08:39:17 +00:00
Faith Ekstrand
01d15d8a38 nak: Revert "nak: Handle non-DW-aligned UBO loads" 
This reverts commit 70c9fc66ffab8cb85b37c74b507201097e16da85.  We're now
handling non-DW-aligned UBO loads in NIR where we can handle it a bit
more completely, we don't need to carry the nak_from_nir code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26412>
 2023-11-30 05:05:00 +00:00
Faith Ekstrand
67e6ca1924 nak/nir: Handle CBuf alignment rules 
The NIR lowering is more complete and lets us properly handle 16-bit
loads which, weirdly, require a 4B alignment.

Fixes: bda208665f ("nak: Handle non-DW-aligned UBO loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26412>
 2023-11-30 05:05:00 +00:00
Timothy Arceri
57acffbba8 glsl: remove GLSL IR lower_named_interface_blocks() 
We now use a NIR based lowering pass instead.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26001>
 2023-11-30 03:45:08 +00:00
Timothy Arceri
cdf0ed8960 glsl: use the nir based lower_named_interface_blocks() 
Because we are now doing the lowering in NIR we need to move the code
that sets the compact flag on some builtin vars out of the glsl to nir
pass.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26001>
 2023-11-30 03:45:07 +00:00
Timothy Arceri
bedf504d38 glsl: add nir based lower_named_interface_blocks() 
This will be used in the following patch to replace the GLSL IR
version of this pass.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26001>
 2023-11-30 03:45:07 +00:00
Faith Ekstrand
5311d8713d nak: Implement scan/reduce on booleans 
We could use the lowering in nir_lower_subgroups for this but it's a lot
more complicated than we need and uses quad_any/all which we don't have.

Fixes: cca40086c6 ("nak: Lower scan/reduce in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26411>
 2023-11-30 02:50:25 +00:00
Eric Engestrom
fc30a29bd6 docs/calendar: add 23.3.x releases 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26405>
 2023-11-29 21:05:45 +00:00
Eric Engestrom
e2cd0ece86 docs: update calendar for 23.3.0 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26405>
 2023-11-29 21:05:45 +00:00
Yiwei Zhang
3475c8cc41 venus: scrub msaa sample mask only with valid msaa state 
No crash in dEQP-VK.api.pipeline.pipeline_invalid_pointers_unused_structs.graphics

Fixes: 417437c715 ("venus: pipeline fixes for VK_EXT_extended_dynamic_state3")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26404>
 2023-11-29 20:49:29 +00:00
Pierre-Eric Pelloux-Prayer
b9f4e3c39b Revert "radeonsi: decrease PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS to 1024" 
This reverts commit 03353bd752.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10222
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26401>
 2023-11-29 19:33:48 +00:00
Sagar Ghuge
4ebad93c9c anv,hasvk: Use uint32_t for queue family indices 
Vulkan API uses uint32_t for the queue family indices.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26387>
 2023-11-29 19:07:17 +00:00