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Author SHA1 Message Date
Marek Olšák 9d9cfd89da ac/nir/tess: compute the number of remapped VRAM outputs in common code 
This unifies it for both drivers.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák ea70060826 ac/nir/tess: stop using tes_inputs_read / tes_patch_inputs read for TCS & TES 
use ac_nir_tess_io_info instead

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák c38bc4824f ac/nir/tess: apply no_varying to ac_nir_tess_io_info 
This has the effect that no_varying is finally honored for per-patch
outputs, skipping VMEM stores that TES doesn't read.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák f2c48652da nir: add shader_info::tess::tcs_*outputs_read_by_tes* 
Gather no_varying for AMD.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák 42445e271e radv,radeonsi: use ac_nir_tess_io_info for LDS size computation 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák c678844ccb ac/nir/tess: move LDS and VMEM output masks into a new info structure 
This will replace LDS and VMEM output size computations in drivers.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák f9c2a01f6a ac/nir/tess: indent a block for nir_if 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák d967266edd ac/nir/tess: if all tess levels are 0, skip per-vertex TCS output stores 
This is done for all chips.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák c1237256cb ac/nir/tess: execute the tess level workgroup vote on all chips 
It will be used to skip stores for discarded patches.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák 9c16228359 ac/nir/tess: write TCS per-vertex outputs to memory as vec4 stores at the end 
This improves write throughput for TCS outputs. It follows the same idea
as attribute stores in hw GS. The improvement is easily measurable with
a microbenchmark.

It also has the advantage that multiple output stores to the same address
don't result in multiple memory stores. Each output components gets only
one memory store at the end of the shader.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák 509f0e62ad ac/nir/tess: allow passing explicit patch_offset to VMEM/LDS offset calculations 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák a59464b6e3 radv,radeonsi: precompute and pass TCS per-vertex output stride via a user SGPR 
It's a stride of 1 output, which isn't 16. It's 16 * num_threads,
aligned to 256.

tcs_offchip_layout has 5 unused bits, so let's use them.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák 742227c65c radv,radeonsi: make TCS_OFFCHIP_LAYOUT_NUM_PATCHES not off by one 
We never use 128 anyway.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák 8d3e3c72e0 radv,radeonsi: merge PATCH_CONTROL_POINT & OUT_PATCH_CP into 1 field 
One is only used by TCS, the other is only used by TES.
Use the same field for both, call it PATCH_VERTICES_IN.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:39 +00:00
Marek Olšák 534b282573 ac/nir/tess: adjust memory layout of TCS outputs to have aligned store offsets 
There is a comment that explains it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:38 +00:00
Marek Olšák 80236f2367 ac/nir/tess: add if/endif for HS threads in NIR instead of ACO/LLVM 
This just removes the if/endif wrapping for LLVM, and hopefully the ACO
change does the same thing.

ACO had redundant code in endif_merged_wave_info, which is removed here.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:38 +00:00
Marek Olšák cd366b57d9 ac/nir: implement load_subgroup_id/local_invocation_index for TCS on gfx6-10.x 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
 2025-06-07 16:29:38 +00:00
Eric Engestrom b937d8be9d docs: add sha sum for 25.1.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35401>
 2025-06-07 14:19:55 +00:00
Eric Engestrom 5c25b09002 docs: add release notes for 25.1.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35401>
 2025-06-07 14:19:55 +00:00
Eric Engestrom 1f787ff64e docs: update calendar for 25.1.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35401>
 2025-06-07 14:19:55 +00:00
llyyr c8bd9ac789 brw: don't unconditionally print message on instance creation 
This would cause Mesa to print this message even if an Intel GPU is just
being enumerated by a Vulkan application. For example, `vulkaninfo
--summary`.

Fixes: 52f73db5b7 ("brw: implement read without format lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35396>
 2025-06-07 13:59:22 +00:00
Pavel Ondračka 16dbcd9b04 r300/ci: add two flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35400>
 2025-06-07 12:12:41 +02:00
Valentine Burley c6aad1b4c2 khronos-update: Add missing Vulkan Video headers 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35384>
 2025-06-07 05:52:21 +00:00
Guilherme Gallo f61fe79fc0 ci/turnip: Update a couple of flaky tests on a660-vk 
Got a consecutive timeout in two different `a660-vk` jobs on
`dEQP-VK.subgroups.clustered.compute.subgroupclusteredmax_u64vec4_requiredsubgroupsize`
test.

Analyzed the CI quality stats dashboard [1] (via job name filter) and also
found a flaky
`dEQP-VK.clipping.user_defined.clip_cull_distance.vert_tess_geom.1_7` on
the same job

[1] https://ci-stats-grafana.freedesktop.org/goto/1ai94GLHR?orgId=1

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35377>
 2025-06-07 04:28:49 +00:00
Rob Clark 242f677d20 freedreno: A couple features.txt updates 
Just catching up with reality.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark 0b20bddb8a freedreno: correct resource usage check 
Usage is not a bitmask.  This was causing us to not pick cached-coherent
for staging read buffers (ie. clEnqueueReadBuffer() and friends).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark 95fede0126 freedreno: Use non-draw batches for compute contexts 
We don't want opencl profiling related queries to create "draw" batches,
as we'd end up with three batches per grid.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark 014b2308c0 freedreno: Fix compute caps 
Get subgroup_sizes and max_compute_units from dev info.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark 57eb3529ac freedreno: Don't autotune if we are already sysmem 
If we've already picked sysmem (for example, non-draw batches) no need
to autotune.  Avoids autotune for compute-only workloads, for example.
Cuts down on per-batch overhead when we get a lot of single grid batches.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Rob Clark c5e2e26f49 freedreno: Avoid repeated device lookup 
fd_device_gen() calls fd_dev_info_raw() which loops over all the device
table entries.  No need to do this for every batch.  And we _especially_
don't want to do this per-batch when rusticl cl profiling mode triggers
a batch flush for every launched kernel.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35371>
 2025-06-06 21:15:21 +00:00
Caleb Callaway 111005066d anv: Increase max VBs to 33 on Gen11+ 
Prior to Gen 11, we had to upload a bunch of SGVs
(FirstVertex, BaseVertex, BaseInstance, DrawID) via
3DSTATE_VERTEX_BUFFERS.

For Gen11+, we upload via 3DSTATE_SGVS_2 instead.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35376>
 2025-06-06 19:32:35 +00:00
Mel Henning 5f0e4a7605 nak,nir: Stop using std::mem::zeroed() 
We can replace all of these with safe alternatives if we ask bindgen for
implementations of Default.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35390>
 2025-06-06 18:58:35 +00:00
Mel Henning d15b5fadbb nir/divergence_analysis: Update LCSSA comment 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35271>
 2025-06-06 18:15:05 +00:00
Caio Oliveira 80fb555718 brw: Fix MAD instruction usage in spilling logic 
The intention here is to build a SIMD8 value, that will be expanded
as needed -- just like the SHL/ADD case, but with a single instruction.

Found when the was triggering invalid MAD with SIMD32 (that gets compressed)
*and* with overlapping destination and source *and* which would cause
conflict when divided into two SIMD16.

Fixes: 338273dedd ("brw/reg_allocate: Optimize spill offset calculation using integer MAD")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35302>
 2025-06-06 15:31:50 +00:00
Lionel Landwerlin 9c0ff88e8d vulkan: dump headers/registry to 1.4.317 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35382>
 2025-06-06 14:38:17 +00:00
Lionel Landwerlin 49def5ca9d spirv: bump headers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35382>
 2025-06-06 14:38:17 +00:00
Boris Brezillon bb07343c28 pan/image: Start checking image view consistency 
We recently found a weird case where an image was re-interpreted with
a format that had a bigger size than the image format, which led the
resulting texture descriptor to have a size that was bigger than what
the plane descriptors were covering.

Let's make sure this sort of unexpected use don't slip through in the
future by introducing basic image view consistency checks.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35317>
 2025-06-06 14:16:43 +00:00
Boris Brezillon eb476fd2c6 panfrost: Make the MTK detiling more robust 
There are several problems in the current logic:

- it doesn't account for the WSI stride, and just assumes things are
  tightly packed and the resource extent is aligned on a tile
- the format re-interpretation done in panfrost_mtk_detile_compute()
  where the view format and the image format have a different block size
  is not supposed to be supported, and that's something we'd like
  to enforce now
- we write to textures that may have no descriptors bound to. This works
  thanks to the robustness behind image stores/loads, but we'd probably
  rather discard a bunch of instructions when Y/UV planes are copied
  separately
- the linear to tiled coordinates conversion can be simplified by using
  a combination of local_invocation_id+workgroup_id instead of the
  global_invocation_id

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35317>
 2025-06-06 14:16:43 +00:00
Boris Brezillon a87805fdd8 panfrost: Draw a clear line between AFBC and MTK_TILED conversion shaders 
Those two types are completely different, and they don't use the same
key attributes. Let's provide two different helpers, and place the key
bits that are AFBC-specific into an struct inside a union. We also add
the modifier to the key to prevent AFBC/MTK_TILED collisions.

Not only this make things clearer, but we also no longer compile
MTK detiling shaders when AFBC shaders are requested (or the other way
around).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35317>
 2025-06-06 14:16:43 +00:00
Lars-Ivar Hesselberg Simonsen e6d53fc1d8 panvk: Add FS read support for PrimitiveID 
Adds support for reading PrimitiveID in a fragment shader assuming the
previous shader was vertex.

If support for shaders that can modify PrimitiveID is added, additional
changes will be required.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35367>
 2025-06-06 13:54:57 +00:00
Lars-Ivar Hesselberg Simonsen 49a7b1a5b8 panvk: Fix unsupported LogicOp NOOP blending 
For formats that do not support LogicOps, NOOP should be treated as
COPY. This was implemented in nir/lower_blend, but an optimization in
PanVK would trigger for all NOOP that stopped this from happening.

This commit limits the NOOP optimization to supported formats.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35367>
 2025-06-06 13:54:57 +00:00
Mary Guillemard 8953c13b15 panfrost: Remove pan_indirect_dispatch 
Now that we use a precomp shader for indirect dispatch,
we can safely remove this.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Mary Guillemard 2c563781fc panfrost: Enable indirect dispatch support on v6 and v9 
Our CL implementation also handle v6/v9 and pass CTS.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Mary Guillemard 33fed5a20f panfrost: Use panlib indirect dispatch precomp shader in Gallium 
Now that we have an implementation there, we can just call it.

This pass "dEQP-GLES31.functional.compute.indirect_dispatch.*".

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Mary Guillemard 8b4e515ca2 panvk: Implement indirect dispatch on JM 
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Mary Guillemard bf9331b3fe libpan: Add indirect dispatch implementation 
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Mary Guillemard 1abe5d1da9 pan/genxml: Switch pan_merge to a macro 
This switch pan_perge to a macro to keep address space
information when working with OpenCL C.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Mary Guillemard a1b1713b43 panfrost: Make pan_encoder.h CL safe 
Will be used for indirect dispatch.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32839>
 2025-06-06 12:58:21 +00:00
Lionel Landwerlin c9ccb9568f anv: simplify RENDER_SURFACE_STATE parsing 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22524>
 2025-06-06 12:28:42 +00:00
Lionel Landwerlin 1f5a9a5a73 anv: add support for shaderStorageImageReadWithoutFormat through emulation 
Using in shader lowering, only relevant for Gfx9,11,12.0 platforms.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5117
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22524>
 2025-06-06 12:28:42 +00:00