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Faith Ekstrand 9ba70bb1ed vulkan: Expose a vk_cmd_set_rendering_attachment_locations() helper 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
 2024-09-05 17:55:21 +00:00
Faith Ekstrand ea783a96b8 vulkan: Allow pColorAttachmentLocations == NULL in CmdSetRenderingAttachmentLocationsKHR() 
Fixes: fe19405c46 ("vulkan/runtime: handle new dynamic states for attachment remapping")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
 2024-09-05 17:55:21 +00:00
Faith Ekstrand c626be82f4 vulkan: Add a helper for getting VkRenderingAttachmentLocaiontInfoKHR 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
 2024-09-05 17:55:21 +00:00
Faith Ekstrand 0fd0437993 nvk: Add all_linear to nvk_rendering_state 
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
 2024-09-05 17:55:21 +00:00
Faith Ekstrand e533484d06 nvk: Take depth image layer counts from the VkRenderingInfo 
Otherwise OOB layers may render to the wrong layer in the depth image.
While we're here, add the same layer count asserts for color images.

Fixes: 9345b95346 ("nvk: Bind 3D depth/stencil images as 2D arrays")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
 2024-09-05 17:55:21 +00:00
Faith Ekstrand d7d0287237 nvk: Don't do linear<->tiled copies for rendering suspend/resume 
This also fixes a bug where we were potentially emitting copy commands
after we'd called nvk_cmd_buffer_push() but before finishing the current
push.  Rust would have caught this...

Fixes: bca2f13dd8 ("nvk: enable rendering to DRM_FORMAT_MOD_LINEAR images")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
 2024-09-05 17:55:21 +00:00
Erico Nunes 6f3c003433 v3dv: unconditionally expose VK_EXT_queue_family_foreign 
Zink currently requires VK_EXT_queue_family_foreign to set
PIPE_CAP_DMABUF, which is one of the requirements to create a
gbm context.
v3dv already conditionally supported this extension for Android.
As it is now required for Zink in Mesa, move it to the driver's
common set.
This allows v3dv to create gbm contexts with Zink again since
this was made a stricter requirement as a side effect of
ab08b79ef7 ("gbm: use driver check for dmabuf export").

Tested with Zink on a gbm EGL application as well as sway with
the wlroots Vulkan backend, which also requires this extension.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30938>
 2024-09-05 15:44:01 +00:00
Boyuan Zhang d756966a28 radeonsi/vcn/enc:enable hevc cu_qp_delta for vcn2+ 
Set cu_qp_delta based on value passed in, remove hardcoded values.
Only enable this for vcn2+.

V2: diff_cu_qp_delta_depth has to be 0 due to hw limitation
cu_qp_delta needs to be enabled for qp map and rc to work properly.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31007>
 2024-09-05 14:55:12 +00:00
Boyuan Zhang 5330ba8d37 frontends/va: get cu_qp_delta from vaapi 
Get cu_qp_delta_enabled_flag and diff_cu_qp_delta_depth from vaapi interface

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31007>
 2024-09-05 14:55:12 +00:00
Aleksi Sapon 13a2805325 llvmpipe: FlameGraph profiling support 
For use outside Linux.

Enable dumping JIT address mappings and assembly
using an environment variable. Add a script to map
JIT addresses in collapsed stacks, and annotate
assembly dumps with sample counts.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30626>
 2024-09-05 14:19:20 +00:00
Aleksi Sapon 6a3234ee3b llvmpipe: improvements to JIT assembly dump 
Fix disassembly off-by-one instruction bug, add
Aarch64 support, add addresses to symbol names,
cleanup iostream usage.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30626>
 2024-09-05 14:19:20 +00:00
David Rosca af8c680087 vulkan/wsi: Fix stack-use-after-scope in x11_surface_create_swapchain 
drm_image_params and num_modifiers are used outside the if-scope as
wsi_swapchain_init argument.

Fixes: 8f6fca89aa ("meson: delete dri3 build option")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31036>
 2024-09-05 13:18:57 +00:00
David Heidelberg 63781071db panfrost: drop leftover definition after pan_nir_lower_64bit_intrin removal 
Fixes: bd0d3c7b1c ("panfrost: drop pan_nir_lower_64bit_intrin")
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30994>
 2024-09-05 11:02:29 +00:00
Samuel Pitoiset 165c026161 radv: add a helper to write a single vertex descriptor with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Samuel Pitoiset 374abea26b radv: pass use_per_attribute_vb_descs in radv_dgc_params 
This is more like a shader metadata parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Samuel Pitoiset 955f148db1 radv: specialize one more VBO parameter with DGC 
This covers the case when unused VBO bindings are defined with DGC.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Samuel Pitoiset e99ea580f7 radv: fix missing attribute offset with dynamic VS inputs and DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31018>
 2024-09-05 10:29:55 +00:00
Karol Herbst 14ebecd787 clc: fix compilation error with llvm-20 
LLVM commit:
https://github.com/llvm/llvm-project/commit/924a7d83b4287b3b85dd1ca29d2d3e1f0a10ea68

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11814
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30980>
 2024-09-05 09:44:03 +00:00
David Heidelberg d16581652f ci/iris: implement nightly CL testing using piglit on ADL 
Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29516>
 2024-09-05 08:57:51 +00:00
David Heidelberg aaa332a751 ci/freedreno: add Adreno 306/307 occasional timeout 
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31037>
 2024-09-05 17:13:58 +09:00
Zan Dobersek 4c359eae01 tu: use instance indices in RD dump filenames 
Until now the RD dumps were stored in files on a per-device basis, using
the device index but assuming only one Vulkan instance is active. With
multiple active instances, different devices separated across those
instances could end up storing RD dumps into files with the same name.

tu_instance struct now has an index member variable that's assigned upon
creation with an incrementally-increasing global counter value. RD dump
output name now also contains this instance index, avoiding the described
naming collisions.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: f9c4e25483 ("freedreno: add fd_rd_output facilities for gzip-compressed RD dumps")
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30977>
 2024-09-05 08:47:27 +02:00
Lionel Landwerlin aa494cbacf brw: align spilling offsets to physical register sizes 
In commit fe3d90aedf ("intel/fs/xe2+: Fix calculation of spill message
width for Xe2 regs.") we aligned the width of scratch messages to
physical register sizes (32B prior to Xe2, 64B for Xe2+).

But our spilling offsets are computed using the register allocations
sizes which are in units of 32B. That means on Xe2, you can end up
spilling a virtual register allocated at 32B (which we use for surface
state computations with exec_all) and then the spilling of that
register will be emitted in SIMD16, having the upper 8 lanes
overwriting the next spilled register.

We could potentially limit spills to SIMD8 messages on Xe2 (only
writing 32B of data), but we're also unlikely to have all 32B virtual
register spilled next to one another. And if not tightly packed, we
would have 64B registers stored on 2 different cachelines which sounds
inefficient.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fe3d90aedf ("intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.")
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30983>
 2024-09-04 23:05:31 +00:00
Erico Nunes 4f99e84367 docs/ci: pass -D platforms=[] to avoid dependencies 
Since commit 8f6fca89aa ("meson: delete dri3 build option"),
the docs build attempts to find dependencies like xshmfence which
are not found in the current docs image.
Avoid checking for those dependencies by not enabling any platforms,
which will skip the check overall.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31025>
 2024-09-04 22:57:25 +00:00
Sil Vilerino 0190523021 d3d12: Use pipe_h264_enc_seq_param.max_num_ref_frames instead of pipe_video_codec.max_references in SPS 
Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31017>
 2024-09-04 22:07:33 +00:00
Sil Vilerino 22bb1d4a94 d3d12: Use d3d12_video_encoder_get_current_max_dpb_capacity in tex array pool instead of separate constant 
Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31017>
 2024-09-04 22:07:33 +00:00
Sil Vilerino 6e745073dc d3d12: Fix d3d12_video_encoder_get_current_max_dpb_capacity to report actual max slots number in DPB 
Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31017>
 2024-09-04 22:07:33 +00:00
Sil Vilerino 72f4b7f01b d3d12: Remove max_references usage from frontend to reserve barriers array 
Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31017>
 2024-09-04 22:07:33 +00:00
Sil Vilerino 7c8ffc34aa pipe: Add PIPE_H26X_MAX_REFERENCES 
Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31017>
 2024-09-04 22:07:33 +00:00
Jordan Justen f817870aa9 anv: Don't warn about unsupported devices if INTEL_FORCE_PROBE was used 
The user must have used INTEL_FORCE_PROBE to force the device to be
loaded, so they specifically opted-in to enabled unsupported device
support.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31011>
 2024-09-04 12:09:12 -07:00
Jordan Justen ee727d7b66 intel/dev: Add devinfo::probe_forced based on INTEL_FORCE_PROBE 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31011>
 2024-09-04 12:09:08 -07:00
Jordan Justen aaaf9a3b87 anv: Do hasvk devices check first 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31011>
 2024-09-04 12:09:05 -07:00
Jordan Justen 16a835ed3d anv: Drop "not yet supported" warning for Xe2 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31011>
 2024-09-04 12:09:01 -07:00
José Roberto de Souza ca13e35304 anv: Add anv_device_perf_close() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31026>
 2024-09-04 10:04:38 -07:00
José Roberto de Souza 2d216c12fa anv: Drop useless '>= 0' check over a unsigned 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31026>
 2024-09-04 10:04:38 -07:00
José Roberto de Souza 023120d1fc intel/perf: Fix intel_gem.h include 
The intention here was to get include the common intel_gem.h to
get the intel_ioctl() signature.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31026>
 2024-09-04 10:04:38 -07:00
José Roberto de Souza 5d4e319aec anv: Nuke perf_metric 
This is not used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31026>
 2024-09-04 10:04:37 -07:00
Mike Blumenkrantz 8f6fca89aa meson: delete dri3 build option 
this existed for historical reasons, but realistically now it should
be possible to build mesa with dri3 always enabled. additionally,
this check was often used as a substitute for having drm functionality,
which is sort of similar but also not really a direct match

this simplifies a bunch of conditionals and prevents users from footgunnning
themselves into orbit

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30952>
 2024-09-04 14:48:17 +00:00
Mike Blumenkrantz 56ac378454 dril: also create double-buffered configs in swrast fallback 
Fixes: 06d417af80 ("dril: use the super fallback path for software fallback")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31013>
 2024-09-04 14:02:52 +00:00
Mike Blumenkrantz 68a631947f tc: optimize out tracked winsys resolves 
drivers using renderpass tracking can rely on having
pipe_framebuffer_state::resolve + tc_info::has_resolve to indicate
a winsys blit, which means they don't actually need the blit call

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30772>
 2024-09-04 13:06:36 +00:00
Mike Blumenkrantz 3b198d5392 tc: break out blit enqueue to separate function 
no functional changes

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30772>
 2024-09-04 13:06:36 +00:00
Mike Blumenkrantz 5e319b0a3d zink: use tc renderpass optimizing to inline resolves with dynamic render 
this also permits invalidating cubfs that use inlined resolves

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30772>
 2024-09-04 13:06:36 +00:00
Mike Blumenkrantz 2c700bb842 zink: create a surface for resolve resources 
this can be reused since the state tracker doesn't give a surface

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30772>
 2024-09-04 13:06:36 +00:00
Mike Blumenkrantz cd7ad7bd7e vk: rename DGC feature to DGC-NV 
this is an NV extension, so it should have NV suffix

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31015>
 2024-09-04 12:27:21 +00:00
Tapani Pälli d5916cb3ca mesa: check for ARB_ES3_compatibility in format checks 
Fixes regressions seen with following tests:

 dEQP-GL45-ES3.functional.negative_api.buffer.read_pixels
 dEQP-GL45-ES3.functional.negative_api.buffer.read_pixels_format_mismatch
 dEQP-GL45-ES31.functional.debug.negative_coverage.get_error.buffer.read_pixels
 dEQP-GL45-ES31.functional.debug.negative_coverage.get_error.buffer.readn_pixels
 dEQP-GL45-ES31.functional.debug.negative_coverage.get_error.buffer.read_pixels_format_mismatch

Fixes: e8226bda60 ("mesa/main: validate desktop gl format/types")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31008>
 2024-09-04 11:54:22 +00:00
Lucas Stach e6c2bf38b1 etnaviv: singlethread shader variant compiles when dumping shaders 
When more than one instance of the shader compiler is running at
once, the output of ETNA_MESA_DEBUG=dump_shaders is almost useless
as output from multiple instances will get interleaved, making it
very hard to parse.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30604>
 2024-09-04 09:13:33 +00:00
Lucas Stach d29dfc180e etnaviv: allow shader machine code dumps in release builds 
There is no reason to hide the shader machine code on release
builds when ETNA_MESA_DEBUG=dump_shaders is specified. This
debug option will dump lots of NIR already, so the machine
code is in good company.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30604>
 2024-09-04 09:13:33 +00:00
Lucas Stach 447ac6d6c6 etnaviv: wire up missing gl_VertexID bits 
While some bits for gl_VertexID were already present in the
compiler, it was still missing in lots of cases. Wire those
up to make gl_VertexID usable.

Fixes piglit spec@!opengl es 3.0@gl_vertexid.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30604>
 2024-09-04 09:13:33 +00:00
Samuel Pitoiset 63112e79ac radv: use compute pipeline metadata for non-indirect DGC pipelines 
The idea is to better abstract loading shader metadata parameters by
using the same layout for indirect/non-indirect compute pipelines.

Graphics support will added later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30987>
 2024-09-04 06:50:38 +00:00
Samuel Pitoiset 9a07b8fa1c radv: store the indirect compute pipeline VA to dgc_cmdbuf 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30987>
 2024-09-04 06:50:38 +00:00
Samuel Pitoiset 81ec193e1b radv: specialize dispatch initiator for compute/task shaders with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30987>
 2024-09-04 06:50:38 +00:00