9a3a1027a6
radeonsi/vcn: Unmap bitstream buffer in radeon_dec_destroy
...
If an error occured, the bitstream buffer may still be mapped when
calling radeon_dec_destroy and this would trigger assert when destroying
the bo.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504 >
2024-12-06 11:24:53 +00:00
ed5794c5e3
radeonsi/vcn: Remove code handling buffer_get_virtual_address failure
...
buffer_get_virtual_address can't return zero.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504 >
2024-12-06 11:24:53 +00:00
5f3a93dacf
frontends/va: Move mjpeg sampling_factor to pipe_mjpeg_picture_desc
...
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32504 >
2024-12-06 11:24:53 +00:00
7a9f14d3c2
panvk: advertise VK_EXT_provoking_vertex
...
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com >
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273 >
2024-12-06 10:40:03 +00:00
fec20b26dd
panvk: set provoking vertex in fbinfo
...
This must match the value set in TILER_CONTEXT. Fixes
dEQP-VK.rasterization.flatshading.*, which were failing previously
because we were setting first_provoking_vertex to true in the tiler
descriptor and false in fbinfo.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com >
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273 >
2024-12-06 10:40:03 +00:00
c324790ca8
panvk: treat provoking vertex as dynamic state
...
Needed for VK_EXT_provoking_vertex, and makes the fbinfo provoking
vertex requirements easier to follow.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com >
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273 >
2024-12-06 10:40:03 +00:00
c383859a07
panvk: refactor fbinfo into a temp var in get_tiler_desc
...
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com >
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32273 >
2024-12-06 10:40:03 +00:00
1a90c3102b
radeonsi/vcn: Don't allow encoding H264 B-frame references
...
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12242
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32479 >
2024-12-06 10:00:47 +00:00
cd8ad03364
frontends/va: Store picture type for buffers in encode DPB
...
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32479 >
2024-12-06 10:00:47 +00:00
c2f8f20ef7
radv,driconf: Apply DOOM Eternal/idTech workarounds for Indiana Jones
...
It's based on idTech and exhibits the same idTech bugs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32521 >
2024-12-06 09:21:17 +00:00
047049dcb5
nir: Fix the spelling of compare
...
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com >
Reviewed-by: Connor Abbott <cwabbott0@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32189 >
2024-12-06 08:42:36 +00:00
b79994e92d
nir,ir3: Add icsel_eqz
...
In IR3 `sel.b32` works based on the 0 so add `icsel_eqz` to fuse the
cmp and sel that we'd otherwise need.
total Instruction Count in shared programs: 1112814 -> 1110473 (-0.21%)
Instruction Count in affected programs: 162701 -> 160360 (-1.44%)
helped: 81
HURT: 29
Instruction count are helped.
total MOV Count in shared programs: 86777 -> 88671 (2.18%)
MOV Count in affected programs: 28119 -> 30013 (6.74%)
helped: 1
HURT: 292
Mov count are HURT.
total COV Count in shared programs: 15070 -> 14962 (-0.72%)
COV Count in affected programs: 5770 -> 5662 (-1.87%)
helped: 76
HURT: 2
Cov count are helped.
total Last helper instruction in shared programs: 592729 -> 590638 (-0.35%)
Last helper instruction in affected programs: 91331 -> 89240 (-2.29%)
helped: 30
HURT: 1
Last helper instruction are helped.
total Instructions with SS sync bit in shared programs: 29336 -> 29546 (0.72%)
Instructions with SS sync bit in affected programs: 4702 -> 4912 (4.47%)
helped: 8
HURT: 43
Instructions with ss sync bit are HURT.
total Estimated cycles stalled on SS in shared programs: 111590 -> 112401 (0.73%)
Estimated cycles stalled on SS in affected programs: 27708 -> 28519 (2.93%)
helped: 21
HURT: 61
Estimated cycles stalled on ss are HURT.
total cat1 instructions in shared programs: 101933 -> 103695 (1.73%)
cat1 instructions in affected programs: 35804 -> 37566 (4.92%)
helped: 18
HURT: 290
Cat1 instructions are HURT.
total cat2 instructions in shared programs: 380299 -> 377499 (-0.74%)
cat2 instructions in affected programs: 128609 -> 125809 (-2.18%)
helped: 322
HURT: 0
Cat2 instructions are helped.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com >
Reviewed-by: Connor Abbott <cwabbott0@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32189 >
2024-12-06 08:42:36 +00:00
aad0aa0a9c
nir/algebraic: turn u{ge,lt} a, 1 to i{ne,eq} a, 0
...
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com >
Reviewed-by: Connor Abbott <cwabbott0@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32189 >
2024-12-06 08:42:36 +00:00
6b671d4dab
radv: remove redundant drirc for incorrect dual-source blending
...
The pass that lowers PS outputs has been rewritten since 45d8cd037asamuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32514 >
2024-12-06 07:54:23 +00:00
e1bb53bb3c
nir/algebraic: Optimize some trivial bfi
...
In fossil-db, one big compute shader on Hogwarts Legacy is helped for
spills and fills. It has a lot of instances of bfi(0x3f, a, a).
On Tiger Lake and Skylake, a compute shader in Unicom that has a
single instance of this pattern is hurt for spills and fills. I think
this is just due to non-determinism in the register allocation
algorithm.
shader-db:
All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 16992643 -> 16992548 (<.01%)
instructions in affected programs: 17533 -> 17438 (-0.54%)
helped: 33 / HURT: 0
total cycles in shared programs: 914313986 -> 914316238 (<.01%)
cycles in affected programs: 3734544 -> 3736796 (0.06%)
helped: 26 / HURT: 6
fossil-db:
Lunar Lake, Meteor Lake, DG2, and Ice Lake had similar results. (Lunar Lake shown)
Totals:
Instrs: 208952780 -> 208952537 (-0.00%)
Send messages: 10934879 -> 10934875 (-0.00%)
Cycle count: 30988230904 -> 30988228660 (-0.00%); split: -0.00%, +0.00%
Spill count: 534864 -> 534843 (-0.00%)
Fill count: 667081 -> 667068 (-0.00%)
Max live registers: 65686656 -> 65686624 (-0.00%)
Non SSA regs after NIR: 244185358 -> 244185335 (-0.00%)
Totals from 3 (0.00% of 704834) affected shaders:
Instrs: 4708 -> 4465 (-5.16%)
Send messages: 234 -> 230 (-1.71%)
Cycle count: 264382 -> 262138 (-0.85%); split: -0.88%, +0.03%
Spill count: 91 -> 70 (-23.08%)
Fill count: 73 -> 60 (-17.81%)
Max live registers: 647 -> 615 (-4.95%)
Non SSA regs after NIR: 3957 -> 3934 (-0.58%)
Tiger Lake
Totals:
Instrs: 230516919 -> 230515185 (-0.00%); split: -0.00%, +0.00%
Send messages: 12657684 -> 12657680 (-0.00%)
Cycle count: 23060318600 -> 23060279758 (-0.00%); split: -0.00%, +0.00%
Spill count: 548462 -> 548446 (-0.00%); split: -0.00%, +0.00%
Fill count: 582304 -> 582294 (-0.00%); split: -0.00%, +0.00%
Scratch Memory Size: 19538944 -> 19539968 (+0.01%)
Max live registers: 41713622 -> 41713593 (-0.00%)
Non SSA regs after NIR: 260667939 -> 260667712 (-0.00%); split: -0.00%, +0.00%
Totals from 174 (0.02% of 794323) affected shaders:
Instrs: 158346 -> 156612 (-1.10%); split: -1.13%, +0.04%
Send messages: 14330 -> 14326 (-0.03%)
Cycle count: 24859875 -> 24821033 (-0.16%); split: -0.32%, +0.16%
Spill count: 183 -> 167 (-8.74%); split: -9.29%, +0.55%
Fill count: 284 -> 274 (-3.52%); split: -7.39%, +3.87%
Scratch Memory Size: 9216 -> 10240 (+11.11%)
Max live registers: 12587 -> 12558 (-0.23%)
Non SSA regs after NIR: 164466 -> 164239 (-0.14%); split: -0.16%, +0.02%
Skylake
Totals:
Instrs: 158904982 -> 158903764 (-0.00%)
Send messages: 8490500 -> 8490496 (-0.00%)
Cycle count: 19732284279 -> 19732345496 (+0.00%); split: -0.00%, +0.00%
Spill count: 519127 -> 519115 (-0.00%)
Fill count: 594283 -> 594290 (+0.00%); split: -0.00%, +0.00%
Max live registers: 33708764 -> 33708739 (-0.00%)
Non SSA regs after NIR: 169377234 -> 169377007 (-0.00%); split: -0.00%, +0.00%
Totals from 174 (0.03% of 648725) affected shaders:
Instrs: 160391 -> 159173 (-0.76%)
Send messages: 14354 -> 14350 (-0.03%)
Cycle count: 24776486 -> 24837703 (+0.25%); split: -0.07%, +0.32%
Spill count: 332 -> 320 (-3.61%)
Fill count: 587 -> 594 (+1.19%); split: -0.17%, +1.36%
Max live registers: 12709 -> 12684 (-0.20%)
Non SSA regs after NIR: 166557 -> 166330 (-0.14%); split: -0.16%, +0.02%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32493 >
2024-12-05 21:39:07 +00:00
04bdbeec31
intel/dev/xe: Fix access to eu_per_dss_mask
...
DRM_XE_TOPO_EU_PER_DSS and DRM_XE_TOPO_SIMD16_EU_PER_DSS can be any
number of bytes long but it was assuming it was always 4 bytes long.
That was not a issue because Xe KMD return 4 bytes even if only needs
1 or 2 bytes but that is a problem with our HW simulator that was
returning 2 bytes.
Fixes: a24d93aa89lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32307 >
2024-12-05 20:30:44 +00:00
371b7a9b0d
anv: set pipeline flags correct for imported libs
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 3d49cdb71eivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32507 >
2024-12-05 19:53:34 +00:00
6e396b400a
anv: fix missing bindings valid dynamic state change check
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 9ddd296cd3ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32507 >
2024-12-05 19:53:34 +00:00
266dfb15c1
docs/envvars: Combine WGL sections
...
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32316 >
2024-12-05 19:46:38 +00:00
f447e31daa
docs/envvars: Remove mention of IRIS_ENABLE_CLOVER
...
This went away when clover dropped nir driver support.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32316 >
2024-12-05 19:46:38 +00:00
a2f96667e2
mesa: update more drivers to handle pipe_blit_info swizzle_enable
...
Handle swizzling by falling through to the software path. Swizzle
should be rarely enabled, so this shouldn't affect performance in
most cases.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31378 >
2024-12-05 18:27:37 +00:00
3da4a404ae
aux: add support for dumping the swizzle in pipe_blit_info
...
Just some additional debug code for the new blit swizzle feature.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31378 >
2024-12-05 18:27:37 +00:00
b81aefcc19
mesa: when blitting between formats clear any unused components
...
If the state tracker chooses to implement one format with a more
general one (e.g. GL_ALPHA implemented with GL_RGBA) we end up
in a situation where some components should be ignored. Readpix
handles this correctly, but blit does not, which means that if
we blit between different formats we can end up writing garbage
into some components. Work around this by adding an explicit
swizzle to the pipe_blit_info struct, which can re-arrange elements
and/or put 0 or 1 into appropriate channels, and use this to
set the appropriate values into unused channels via the sampler
view.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31378 >
2024-12-05 18:27:37 +00:00
9f69f7a66d
panvk: free preload-shaders after compiling
...
These shaders are created using nir_builder_init_simple_shader(), which
allocates using a NULL ralloc-parent, so ralloc_free should be the right
function to free them with.
Fixes: 0bc3502ca3boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32486 >
2024-12-05 17:45:16 +00:00
43738a9a94
vulkan/meta: plug a couple of memory leaks
...
We create NIR shaders here, and we need to free them when we're done with
them as well.
These shaders are created using nir_builder_init_simple_shader(), which
allocates using a NULL ralloc-parent, so ralloc_free should be the right
function to free them with.
Fixes: 514c10344eboris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32486 >
2024-12-05 17:45:16 +00:00
3aad0afc30
teflon/tests: Also use the cache for models in the test suite
...
To speed things up now that we have more models under testing.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32485 >
2024-12-05 17:02:27 +00:00
74239aeb77
teflon/tests: Add support for models with float inputs and outputs
...
Ended up deciding to drop C++ collections and use instead C pointers
because the template use was starting to get ridiculous.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32485 >
2024-12-05 17:02:27 +00:00
f21d8af43a
teflon: Don't crash when a tensor isn't quantized
...
We don't support yet hardware that can deal with floats, but it is
better not to crash.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32485 >
2024-12-05 17:02:27 +00:00
a548b17b4e
teflon: Rename model tests so they aren't skipped by gtest-runner
...
The regular expression engine in gtest-runner was matching more tests
than we wanted, so we weren't testing all we thought.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32485 >
2024-12-05 17:02:26 +00:00
1e117478d4
teflon: Support tests with inputs with less than 4 dims
...
Needed in models such as YOLOX.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32485 >
2024-12-05 17:02:26 +00:00
140150083e
teflon: Add tests for the YOLOX model
...
The model was generated from:
https://github.com/Megvii-BaseDetection/YOLOXa (Apache License 2.0)
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32485 >
2024-12-05 17:02:26 +00:00
8d3d35bf05
frontends/va: Add support for VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME_3
...
Reviewed-by: Leo Liu <leo.liu@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32113 >
2024-12-05 16:34:09 +00:00
80c0d2718c
anv: report formats supported by the common bvh framework
...
Enables DXR 1.1 with vkd3d-proton
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com >
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32487 >
2024-12-05 15:54:10 +00:00
aba90c1523
panfrost: check afbc status in panfrost_query_compression_modifiers
...
In panfrost_query_compression_modifiers we need to ignore AFBC
modifiers if the device does not support AFBC. In order to avoid
duplicating code, we do this by calling panfrost_walk_dmabuf_modifiers
with a flag that indicates we do not want AFRC modifiers.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32406 >
2024-12-05 14:54:09 +00:00
dfc2f054b6
radeonsi/ci: update navi31 failures
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
ed4606a062
radeonsi/ci: remove --slow
...
The tests were split or reduced in glcts.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
c0ccae84a7
radeonsi/ci: remove most flakes and some skips, update navi31 failures
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
af618dd907
radeonsi/ci: stop using a global flakes list, only use a per-chip flakes list
...
We need to start treating flakes as fails and they are likely different
between chips.
I removed the gfx9 flakes file and renamed the original flakes file
to gfx6-tahiti-flakes.csv, but it would be better to add a new flakes
file for each generation we test.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
3ff8111fc6
radeonsi/ci: handle glinfo errors better
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
738a501e92
radeonsi: don't compute total_direct_count in si_draw if it's unused
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
ed372d4b7c
radeonsi: try to fix Navi14 regression in debug builds
...
Assertion failure:
../src/gallium/drivers/radeonsi/si_state_shaders.cpp:1369: unsigned int si_get_input_prim(const
si_shader_selector*, const si_shader_key*, bool): Assertion `gs->stage == MESA_SHADER_VERTEX' failed.
Fixes: 7e959864b2mdaenzer@redhat.com >
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
a3c293cdcd
radeonsi: revert to always returning true for load_cull_any_enabled_amd
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
511a637a5c
radeonsi: pass cull face state via user SGPRs for shader culling
...
The culling code always computes the determinant for culling zero-area
triangles, so passing the state via user SGPRs doesn't really add much
shader code to justify having shader variants for front/back face
culling that uses the same determinant.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32288 >
2024-12-05 12:07:06 +00:00
ca9bf43d0b
nir,asahi: make argument alignment configurable
...
this is more flexible. Mali needs 32-bit alignment, for example.
I added an option struct in case we need to make this a callback or something
later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32398 >
2024-12-05 10:58:51 +00:00
0d77e91ca3
nir/opt_load_store_vectorize: match amul like imul
...
for AGX, we preserve amul all the way until fusing address modes in order to be
able to fuse effectively. so the load/store vectorizer wouldn't vectorize before
fusing.
however, after fusing we get fused intrinsics which are tricky to teach the
vectorizer about as their semantics are pretty subtle. so we can't vectorize
after, either.
the easiest solution is to teach the vectorize about amul, which can always be
replaced by imul for our pattern matches.
this fixes certain cases of vectorization in OpenCL kernels on asahi.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32398 >
2024-12-05 10:58:51 +00:00
77d4ed0a01
nir/opt_algebraic: optimize sign bit manipulation
...
libclc loves to generate the iand(0x7fffffff) pattern. ior/ixor patterns are
added for completeness.
Shaves 4 instructions off libclc vec4 normalize.
v2: Loop over the bit sizes (Georg).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com > [v1]
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32398 >
2024-12-05 10:58:51 +00:00
be049e1c14
nir/search_helpers: handle bcsel in is_only_used_as_float
...
this lets algebraic see through chains of instructions.
v2: Limit recursion depth (Georg).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <marek.olsak@amd.com > [v1]
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32398 >
2024-12-05 10:58:51 +00:00
ecc4d5da67
i915/ci: update CI expectations
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32494 >
2024-12-05 09:35:43 +00:00
19231c7ae3
pan: s/NIR_PASS_V/NIR_PASS/
...
Move away from NIR_PASS_V() like other drivers have done long ago.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: Chia-I Wu <olvaffe@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32480 >
2024-12-05 08:49:45 +00:00
b47cf63cca
panvk: s/NIR_PASS_V/NIR_PASS/
...
Move away from NIR_PASS_V() like other drivers have done long ago.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: Chia-I Wu <olvaffe@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32480 >
2024-12-05 08:49:45 +00:00
David Rosca