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194633 Commits

Author SHA1 Message Date
Eric Engestrom 90d692bd32 zink+radv/ci: set DRIVER_NAME=zink-radv to allow using common expectation files 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36648>
 2025-08-14 16:07:04 +00:00
Eric Engestrom 3a211679f7 softpipe/ci: drop asan fails that are already tracked as normal fails 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36648>
 2025-08-14 16:07:04 +00:00
Eric Engestrom 6ea6682384 lavapipe/ci: drop asan fails that are already tracked as normal fails 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36648>
 2025-08-14 16:07:04 +00:00
Eric Engestrom 1b88e4a262 ci: set DRIVER_NAME in jobs that are implicitly inheriting skip lists 
They were getting these through setting `GALLIUM_DRIVER`, which the next
commit removes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36648>
 2025-08-14 16:07:03 +00:00
Eric Engestrom f6f091b9a6 softpipe/ci: document fixed tests 
Unrelated to this MR, just noticed now.

They are likely missed by the current fraction on that job, which is why
this wasn't noticed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36648>
 2025-08-14 16:07:03 +00:00
Mike Blumenkrantz 117ac6ac0a tc: remove user cbuf uploads 
this is no longer supported (drivers should set prefer_real_buffer_in_constbuf0)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:48 +00:00
Mike Blumenkrantz f967a85f64 mesa/st: rework thread scheduler handling + add dispatch tracking 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz b8cd48e8e8 gallium: always upload cbuf0 when cap is set 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz 203ac73374 gallium: set prefer_real_buffer_in_constbuf0 for all drivers using tc 
this isn't really a functional change since tc was always doing
cbuf uploads anyway

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz 04c505c200 zink: destroy u_uploaders earlier in context destroy 
these might get defer-deleted onto the batch states, so ensure they
don't leak in that way

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz cbb6e0277f r600: stop using util_set_vertex_buffers 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz 2d1758242f r300: stop using util_set_vertex_buffers 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz 9fd27814f1 freedreno: stop using util_set_vertex_buffers 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz e4da10b4cb tc: add a function to check the internal buffer lists 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:47 +00:00
Mike Blumenkrantz 5d8ccf5986 tc: break out buffer list busy check 
no functional changes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:46 +00:00
Mike Blumenkrantz a7fd3b454b util/tc: don't print END_BATCH in debug 
this is a garbage string anyway

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:46 +00:00
Mike Blumenkrantz 097d953492 mesa/st: check for tc on context create 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:45 +00:00
Mike Blumenkrantz 425c1116de mesa: add a ctx param to _mesa_bufferobj_release_buffer 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:44 +00:00
Mike Blumenkrantz 4b8106ba4d mesa: make _mesa_bufferobj_release_buffer static 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36715>
 2025-08-14 12:47:44 +00:00
Gert Wollny b0468b5560 r600/sfn: remove extra slot of AR use 
Since we split the address load the extra slot reservation
for an address register load is no longer needed.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36742>
 2025-08-14 11:58:04 +00:00
Gert Wollny 5d0f212d81 r600/sfn: Fix AR use tracking off-by-one error 
The evauation of loading the AR register was off by one, so that
splitting an ALU group could actually happen after AR was loaded
resulting in a failure to lower to assembly.

Fixes: d617052db6 ("r600/sfn: take address loads into account when scheduling")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36742>
 2025-08-14 11:58:04 +00:00
Gert Wollny 63c801e8c2 r600/sfn: When splitting an ALU CF update possible start of next CF 
Without this update a very long ALU block may not be splitted as
required and lowering to assembly may fail because the maximum
supported length of a ALU CF is overrun.

Fixes: 6aafa2bb49 ("r600/sfn: Split ALU blocks in scheduler to fit into 128 slots")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36742>
 2025-08-14 11:58:04 +00:00
Lionel Landwerlin 381cb2cabd anv: fix R64* vertex buffer format support 
Disabled by mistake :(

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5c7397c751 ("anv: add mapping for VBO formats in format mapping")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36771>
 2025-08-14 08:34:00 +00:00
Iván Briano 35190aac91 anv: dirty descriptor state on CmdSetDescriptorBufferOffets 
Calling vkCmdBindDescriptorBuffersEXT() does not invalidate previously
set descriptor sets. Move the state dirtying to
vkCmdSetDescriptorBufferOffets.

Fixes: ab7641b8dc ("anv: implement descriptor buffer binding")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36768>
 2025-08-14 07:05:31 +00:00
Iván Briano 382b8e3aa2 anv: check for pending_db_mode when dirtying descriptor mode 
If an application switches back and forth between descriptor sets and
descriptor buffers before executing a draw/dispatch, we could end up in
a wrong state due to pending_db_mode not getting updated.

Fixes: ab7641b8dc ("anv: implement descriptor buffer binding")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36768>
 2025-08-14 07:05:31 +00:00
Samuel Pitoiset 0ac7f1888f radv: reduce the combined image/sampler desc size on GFX11+ 
From 96 to 64 due to the 32 bytes descriptor alignment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:30 +00:00
Samuel Pitoiset 897201d710 radv: only write 32 bytes for combined image/sampler on GFX11+ 
It should be slightly more optimal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:30 +00:00
Samuel Pitoiset b6d093c4f5 radv: do not hardcode the combined image/sampler offset in the db path 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:30 +00:00
Samuel Pitoiset f2b5446cc4 radv: use radv_write_sampler_descriptor() for combined image/sampler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:29 +00:00
Samuel Pitoiset 3fb33aada6 radv: optimize the preprocess buffer size for DGC IES compute 
Using the precomputed information.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:49 +00:00
Samuel Pitoiset e527d2d801 radv: pre-compute more information when updating DGC IES 
These information need to consider that pipelines/shaders in the same
IES struct might slightly differ. They will be used to determine the
preprocess buffer size in a better way.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:49 +00:00
Samuel Pitoiset 0db165ebda radv: pass the IES struct when computing the DGC sequence size 
I completely missed that it's required for the application to pass the
IES struct in vkGetGeneratedCommandsMemoryRequirementsEXT. Also any
changes to the IES struct requires to call it again.

This will allow us to do more optimizations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:49 +00:00
Samuel Pitoiset 771d4b55e8 radv: remove redundant push constant size alignment for DGC 
It's already aligned to 16 bytes when the pipeline layout is created.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:48 +00:00
Samuel Pitoiset 3359386145 radv: fix reserving space for emitting push constants with DGC IES 
layout->push_constant_mask is only the DGC push constant mask (ie. the
tokens that are specified), but with IES all push constants are emitted
from the DGC shader. So it should be the total range of push constant.

This used to work by luck due to the preprocess buffer alignment.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:48 +00:00
Job Noorman 23c49ede57 ir3: use isam for txf with LOD 0 
isaml with LOD 0 is equivalent to isam. Use isam if possible because it
needs one less src register.

Totals:
Instrs: 49141575 -> 49109622 (-0.07%); split: -0.07%, +0.00%
CodeSize: 102938312 -> 102865138 (-0.07%)
NOPs: 8464238 -> 8463245 (-0.01%); split: -0.02%, +0.01%
(ss)-stall: 4013710 -> 4014037 (+0.01%); split: -0.00%, +0.01%
(sy)-stall: 16712850 -> 16712860 (+0.00%)
Preamble Instrs: 11120034 -> 11119863 (-0.00%)
Last helper: 11942609 -> 11934226 (-0.07%); split: -0.07%, +0.00%
Cat0: 9320007 -> 9319014 (-0.01%); split: -0.02%, +0.01%
Cat7: 1636810 -> 1605850 (-1.89%)

Totals from 9523 (5.78% of 164705) affected shaders:
Instrs: 7755614 -> 7723661 (-0.41%); split: -0.41%, +0.00%
CodeSize: 15214510 -> 15141336 (-0.48%)
NOPs: 1722109 -> 1721116 (-0.06%); split: -0.11%, +0.05%
(ss)-stall: 807953 -> 808280 (+0.04%); split: -0.00%, +0.04%
(sy)-stall: 3054163 -> 3054173 (+0.00%)
Preamble Instrs: 1653169 -> 1652998 (-0.01%)
Last helper: 2333301 -> 2324918 (-0.36%); split: -0.36%, +0.00%
Cat0: 1888236 -> 1887243 (-0.05%); split: -0.10%, +0.05%
Cat7: 276671 -> 245711 (-11.19%)

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36766>
 2025-08-14 04:47:02 +00:00
Yonggang Luo fc1b26f4dc aco: Fixes warning note: ambiguity is between a regular call to this operator and a call with the argument order reversed 
../../src/amd/compiler/aco_util.h:300:9: note: ambiguity is between a regular call to this operator and a call with the argument order reversed
  300 |    bool operator==(const monotonic_buffer_resource& other) { return buffer == other.buffer; }

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36722>
 2025-08-13 19:49:37 +00:00
Emma Anholt acf226f3a7 tu: Fix the comment about DRM_CAP_SYNCOBJ_TIMELINE support. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
 2025-08-13 18:57:43 +00:00
Emma Anholt 00336bc9c4 tu: Use the common syncobj sync type for the layered timelines. 
Everyone else doing emulated timelines is doing it on top of their base
binary type, and that appears to have been the intent of the shared
emulation layer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
 2025-08-13 18:57:43 +00:00
Emma Anholt 9e61e72e9f vk/runtime: Set GPU_MULTI_WAIT on the drm syncobj type. 
DRM syncobjs always let you wait repeatedly on them, so we can set the
flag in the core instead of having each driver override it once they try
to enable the emulated timeline semaphores.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
 2025-08-13 18:57:42 +00:00
Lorenzo Rossi 7375dfd56d nak/kepler: Refine instruction scheduling 
Previously some KeplerA chips failed various dEQP tests when instruction
scheduling was enabled.
In particular, `memory_model.message_passing` had issues where a
`membar` instruction canceled some in-flight predicate writes, and
`barrier.write_image_tess_control_read_image_compute.image_128_r32_uint`
had issues around the `Cont` instruction.

This patch refines instruction scheduling to better match the output of
nvcc. Fixing the various dEQP failing tests.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13528
Fixes: c35990c4bc ("nak: Add real instruction dependencies for Kepler")
Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36393>
 2025-08-13 18:39:56 +00:00
Tapani Pälli 42088cd602 isl/blorp: handle failing 96bpp linear blit case 
Fix the aux usage assert in blorp for 96bpp linear blit and provide CMF
values for RGB formats supported by isl_format_rgb_to_rgba.

CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13670
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36709>
 2025-08-13 16:09:12 +00:00
Karol Herbst 7251c8121b nak: support bra.u with a upred source on Ampere and newer 
CodeSize: 934788544 -> 924393088 (-1.11%); split: -1.11%, +0.00%
Number of GPRs: 3537163 -> 3537161 (-0.00%)
SLM Size: 840556 -> 840560 (+0.00%)
Static cycle count: 222856984 -> 217707273 (-2.31%); split: -2.31%, +0.00%
Spills to memory: 56645 -> 56648 (+0.01%)
Fills from memory: 56645 -> 56648 (+0.01%)
Spills to reg: 67982 -> 68532 (+0.81%); split: -0.02%, +0.83%
Fills from reg: 80336 -> 80547 (+0.26%); split: -0.03%, +0.29%
Max warps/SM: 3666696 -> 3666700 (+0.00%)

Totals from 33243 (37.94% of 87622) affected shaders:
CodeSize: 666331984 -> 655936528 (-1.56%); split: -1.56%, +0.00%
Number of GPRs: 1739764 -> 1739762 (-0.00%)
SLM Size: 588164 -> 588168 (+0.00%)
Static cycle count: 168348730 -> 163199019 (-3.06%); split: -3.06%, +0.00%
Spills to memory: 56502 -> 56505 (+0.01%)
Fills from memory: 56502 -> 56505 (+0.01%)
Spills to reg: 55951 -> 56501 (+0.98%); split: -0.03%, +1.01%
Fills from reg: 65060 -> 65271 (+0.32%); split: -0.03%, +0.36%
Max warps/SM: 1246864 -> 1246868 (+0.00%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36465>
 2025-08-13 15:46:59 +00:00
Karol Herbst b79e55bed7 nak: relayout opt_uniform_instrs 
I'm touching this code in the next commit, so this makes it easier to
review.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36465>
 2025-08-13 15:46:59 +00:00
Karol Herbst 96f2348bdf nak: add more helpers for predicates 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36465>
 2025-08-13 15:46:59 +00:00
Karol Herbst 475c8f0580 nak: set max_gpr to multiple of 8s 
Optimizations cutting down on GPRs often lead to the akward situations
where RA being more restricted and having to insert more mov instructions
pumping up the instruction counts.

In order to give developers more reliable stats we just set the max_gprs
to the next multiple of 8 including taking hw reserved registers into
account.

This does not impact occupancy in any way despite the increase in gprs.

Totals:
CodeSize: 920980864 -> 914748784 (-0.68%); split: -0.69%, +0.02%
Number of GPRs: 3544248 -> 3879749 (+9.47%)
Static cycle count: 217345431 -> 216414194 (-0.43%); split: -0.50%, +0.07%

Totals from 78493 (89.58% of 87622) affected shaders:
CodeSize: 795883088 -> 789651008 (-0.78%); split: -0.80%, +0.02%
Number of GPRs: 3108571 -> 3444072 (+10.79%)
Static cycle count: 187450578 -> 186519341 (-0.50%); split: -0.58%, +0.08%

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36514>
 2025-08-13 15:29:43 +00:00
Eric Engestrom 708e2edc23 llvmpipe/ci: consistently use x11- prefix for deqp-egl-x11 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36759>
 2025-08-13 15:12:31 +00:00
Eric Engestrom 8a2bf596aa iris/ci: consistently use x11- prefix for deqp-egl-x11 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36759>
 2025-08-13 15:12:31 +00:00
Eric Engestrom 1695328512 freedreno/ci: consistently use x11- prefix for deqp-egl-x11 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36759>
 2025-08-13 15:12:31 +00:00
Valentine Burley e4933d1d90 zink/ci: Document recent flakes on TGL 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
 2025-08-13 14:48:32 +00:00
Valentine Burley 4ba1128600 zink/ci: Add EGL coverage on lavapipe 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
 2025-08-13 14:48:32 +00:00