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Valentine Burley 8f1eca471f radv/ci: Lower concurrency of radv-raven-traces-restricted 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
Valentine Burley 2b50f93fb0 iris/ci: Add a performance traces job on ADL 
Add a new `iris-adl-traces-performance` job, which runs the same set of
traces as the `zink-anv-adl-traces-performance` job.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
Valentine Burley 94a2e0a48d zink/ci: Add a performance traces job on ADL 
Add a new `zink-anv-adl-traces-performance` job, which runs the same set
of traces as the `iris-anv-adl-traces-performance` job.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
Valentine Burley 7d298e3c4b iris/ci: Simplify performance trace template 
The `.profile-traces` template was nearly identical to
`.piglit-performance-base`, differing only by one additional variable.

Since all jobs extending `.piglit-performance-base` were already using
`EGL_PLATFORM: surfaceless`, that setting has been moved into the base
template, allowing `.profile-traces` to be simplified.

This also hides the performance traces jobs from non-Marge pipelines,
as intended.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36074>
 2025-07-14 08:15:25 +00:00
David Rosca f78222dc29 radv/video: Add support for decode tier3 
On VCN5 both distinct and coincide output/dpb are supported. Tier3
(coincide) requires tiling, Tier2 (distinct) also works with linear.
Application can decide which one to use.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35878>
 2025-07-14 07:42:28 +00:00
David Rosca 2d06b43292 radv: Enable tiling for video images on VCN5 
All planes must have the same swizzle mode and no tile swizzle.
Only linear decode target requires the custom height alignment.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35878>
 2025-07-14 07:42:27 +00:00
David Rosca e50ee32876 radv: Don't allow linear tiling for video DPB images 
We don't support linear DPB images and they will currently always
be tiled internally.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35878>
 2025-07-14 07:42:27 +00:00
David Rosca e2554c8f51 ac/surface: Support RADEON_SURF_FORCE_SWIZZLE_MODE on gfx12 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35878>
 2025-07-14 07:42:26 +00:00
Valentine Burley cbb9ebcd82 freedreno/ci: Fix configuration for a618-traces-performance 
The a618-traces-performance job wasn’t actually running performance tests
because it didn’t extend the `.piglit-performance-base` template, which
is what sets the traces to be replayed 150 times.

This also hides the job from non-Marge pipelines, as intended.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36070>
 2025-07-14 06:48:18 +00:00
Valentine Burley d1972be598 ci: Fix trace update script following environment variable changes 
Since 655cf2f553 ("ci: Simplify filter_env_vars using indirect expansion"),
PIGLIT_REPLAY_DEVICE_NAME is declared using `declare -x`, not `export`.

Update the regex in update_traces_checksum.py accordingly. This is safe
for now, as all performance trace jobs currently run in LAVA and use this
declaration style.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36070>
 2025-07-14 06:48:18 +00:00
Samuel Pitoiset a51afbaff8 radv/sdma: fix unaligned 96-bits copies on GFX9 
On SDMA4, when the pitch isn't aligned, the width needs to be scaled
by 3 for 96-bits formats.

On SDMA5+, the pitch is aligned and the driver doesn't need to fallback
to unaligned copies.

CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36067>
 2025-07-14 06:30:55 +00:00
Sagar Ghuge 36172c41dc intel/compiler: Drop unused param from set_memory_address 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36092>
 2025-07-14 03:46:21 +00:00
Caio Oliveira 887642b0f2 intel: Add INTEL_DEBUG=no-vrt 
Add support for disabling the VRT (Variable Register Thread) feature.
The strategy here is to force the old BRW_MAX_GRF limit for the
register allocator (locks the upper limit) and make sure
ptl_register_blocks() always return that amount of blocks (locks
the lower limit).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35781>
 2025-07-13 21:11:02 +00:00
Caio Oliveira 636c37990a iris: Refactor BRW_KEY_INIT to get an iris_prog_base_key 
Avoids passing individual fields of that key repeatedly in
the call-sites.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35781>
 2025-07-13 21:11:00 +00:00
Yogesh Mohan Marimuthu 9fa192ea22 radeonsi: submit cs_preamble_state to as first job in userqueue 
Also any other new context's cs_preamble_state will not be submitted.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:27 +00:00
Yogesh Mohan Marimuthu 0186977988 ac, radeonsi: prepare cs_preamble_state for userq reg shadowing 
register shadowing has to be enabled in CONTEXT_CONTROL packet
in cs_preamble_state for user queue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:27 +00:00
Yogesh Mohan Marimuthu aab890644b radeonsi: reorder if condition in si_init_cp_reg_shadowing() function 
cs_preamble_state can be created before initializing register shadowing
since register shadowing failure means driver failed now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:27 +00:00
Yogesh Mohan Marimuthu 1cb0af6308 radeonsi: add uses_kernelq_reg_shadowing in struct si_context 
sctx->uses_kernelq_reg_shadowing instead of sctx->shadowing.registers
for register shadowing enable check.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:27 +00:00
Yogesh Mohan Marimuthu b55ee5f335 radeonsi: rename sctx->has_graphics to sctx->is_gfx_queue 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:26 +00:00
Yogesh Mohan Marimuthu 761496b49e radeonsi: has_kernelq_reg_shadowing failure means driver failed 
If register shadowing enabling failed, then driver ctx init will
fail instead of disabling register shadowing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:26 +00:00
Yogesh Mohan Marimuthu 0068dbd76b ac: enable kernelq reg shadowing only when userq is disabled 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:25 +00:00
Yogesh Mohan Marimuthu 1000ee3d2f ac,radeonsi,radv: rename register_shadowing_required 
rename register_shadowing_required to has_kernelq_reg_shadowing

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
 2025-07-13 20:05:25 +00:00
Asahi Lina 067d820c9d asahi: Mark KMS exported resource BOs as shared 
Fixes: #13524

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36097>
 2025-07-13 17:43:06 +00:00
Asahi Lina a8f33c35f9 asahi: Add BO handles to resource debug 
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36097>
 2025-07-13 17:43:06 +00:00
Asahi Lina c6e959c871 asahi: Add refcnt assert to agx_bo_unreference() 
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36097>
 2025-07-13 17:43:06 +00:00
Rob Clark 09936883a4 freedreno: dump layout in import path as well 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:54 +00:00
Rob Clark 65931bfc7f freedreno: Move layout to layout_resource_for_handle() 
This is already done for a6xx.  For everyone else move it out of the
common code path and into fd_layout_resource_for_handle().

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:54 +00:00
Rob Clark 329a022894 freedreno/a6xx: Use metadata to resolve INVALID modifier 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:53 +00:00
Rob Clark b4b1573258 freedreno/a6xx: Refactor handle import 
Explicitly layout the resource in all cases, rather than depending on
the partial/incomplete layout that is done in fd_resource_from_handle()
(which will be going away).

Now that we are not YOLOing the layout, it turns up some questionable
assumptions in piglit.  Just mark those xfails for now.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:53 +00:00
Rob Clark 27b0f64b3e freedreno/a6xx: Use handle for explicit layout 
Use the winsys_handle to get the fdl_explicit_layout params rather than
relying on pre-populated layout params.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:53 +00:00
Rob Clark eb7e6a567e freedreno: Pass handle down to layout_resource_for_modifier 
And rename it to layout_resource_for_handle.  The handle contains
additional information such as the pitch/offset for the imported
buffer.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:53 +00:00
Rob Clark 091313c558 freedreno/layout: Remove unneeded shims 
Now that everything is migrated, we can drop the backwards-compat shims.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:52 +00:00
Rob Clark e55c6c5f25 freedreno/a6xx: Convert to fdl6_layout_image 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:52 +00:00
Rob Clark b6e27a9f57 freedreno/a5xx: Convert to fdl5_layout_image 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:52 +00:00
Rob Clark 617969d8a2 freedreno: Move layout init to backends 
Export the existing helper, and call it from the legacy backends which
are not using fdl.

This moves all the layout initialization to the backends (and eventually
to fdl for the backends using that).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:52 +00:00
Rob Clark 4d4745764c freedreno: Pass layout type to backend 
Pass the layout type to setup_slices, renamed to layout_resource, to
move some of the partial layout initialization to the gen specific
backend.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:51 +00:00
Rob Clark 34153d92b5 freedreno: Add helper to initialize layout params 
No point in duplicating this in many places.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:51 +00:00
Rob Clark 43bd9082fa freedreno: Don't call setup_slices for buffers 
We already use fdl_layout_buffer() when the resource is allocated.  But
it was missed to convert fd_resource_resize().  Convert it so there is
no path into ->setup_slices() with something that is a buffer.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:51 +00:00
Rob Clark d485c7b446 turnip: convert to fdl6_layout_image 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:50 +00:00
Rob Clark 15bccc29bd freedreno/layout: Introduce fdl_image_params 
fdl6_layout() (and to a lesser degree) fdl5_layout() is growing an
unwieldly argument list, and it isn't obvious at first glance what
fdl_layout fields should be initialized before calling it.  So split
out a fdl_image_params struct to clean this up.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:50 +00:00
Rob Clark 52f79561e3 freedreno: Misc whitespace cleanups 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
 2025-07-13 17:16:50 +00:00
M Henning ee3d6aa87d nv50_ir: Remove dead variable 
Nothing ever read from fixedReg, so drop it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
 2025-07-13 15:27:33 +00:00
M Henning e573440a5d nv50_ir_ra: Don't coalesce mixed constraints 
It's difficult to handle nodes that have both fixed reg constraints and
compMasks. We may be able to handle some of these in the future, but
skip them for now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
 2025-07-13 15:27:33 +00:00
M Henning b920ff26ee nv50_ir_ra: Use propagated compMask for reg offset 
Previously, we would only offset register ids for LValues that are
directly used in a merge/split instruction, but this is incorrect.
We instead need to apply the offset to all LValues that compMask
has been propagated to. By calcuating this from compMask instead
of figuring it out a second time, we fix that issue and also manage
to simplify the code a bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
 2025-07-13 15:27:32 +00:00
M Henning a46942ce04 nv50_ir_ra: Add constraint movs for split-of-split 
This handles this case similarly to the merge-of-merge fix from c86563c2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
 2025-07-13 15:27:32 +00:00
M Henning 7e653b2eb1 nv50_ir_ra: Remove an assign to lval->compMask 
This code previously stored two rather different masks in compMask:
 1. from merge/splits (calculated in makeCompound), and
 2. in the join root for whatever register was assigned

Since we were already calculating the second type as intfMask where it
is used in checkInterference(), change that function to unconditionally
use intfMask and only use compMask for the first type.

This is functionally equavalent and keeps the types of masks separate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
 2025-07-13 15:27:31 +00:00
Karol Herbst facb048cdb nouveau: move util_framebuffer_init into the driver 
It will get cleaned up later. Maybe.

Also stop setting the context or the reference. It's all dead code now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35806>
 2025-07-13 15:12:48 +00:00
Karol Herbst 5a91e04fa4 nvc0: remove dead surface tracking code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35806>
 2025-07-13 15:12:48 +00:00
Karol Herbst 2a8779f06f nv50,nvc0: Set the texture for 3D blitter surfaces 
This fixes accesses to unitialized data inside pipe_surface_width.

Fixes: 2eb45daa9c ("gallium: de-pointerize pipe_surface")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35806>
 2025-07-13 15:12:48 +00:00
Karol Herbst c96003305e nak: keep phis vectorized if they fit into a register 
Totals:
CodeSize: 936990448 -> 936472720 (-0.06%); split: -0.07%, +0.01%
Number of GPRs: 3539184 -> 3539100 (-0.00%); split: -0.00%, +0.00%
SLM Size: 870756 -> 864200 (-0.75%); split: -0.82%, +0.07%
Static cycle count: 224606486 -> 224173176 (-0.19%); split: -0.21%, +0.02%
Spills to memory: 66542 -> 60425 (-9.19%); split: -9.90%, +0.71%
Fills from memory: 66542 -> 60425 (-9.19%); split: -9.90%, +0.71%
Spills to reg: 68126 -> 68173 (+0.07%)
Fills from reg: 80583 -> 80659 (+0.09%)
Max warps/SM: 3666280 -> 3666276 (-0.00%); split: +0.00%, -0.00%

Totals from 200 (0.23% of 87622) affected shaders:
CodeSize: 5705936 -> 5188208 (-9.07%); split: -10.75%, +1.67%
Number of GPRs: 8160 -> 8076 (-1.03%); split: -1.78%, +0.75%
SLM Size: 40432 -> 33876 (-16.21%); split: -17.76%, +1.54%
Static cycle count: 2163142 -> 1729832 (-20.03%); split: -21.97%, +1.94%
Spills to memory: 30113 -> 23996 (-20.31%); split: -21.88%, +1.57%
Fills from memory: 30113 -> 23996 (-20.31%); split: -21.88%, +1.57%
Spills to reg: 3438 -> 3485 (+1.37%)
Fills from reg: 3836 -> 3912 (+1.98%)
Max warps/SM: 9064 -> 9060 (-0.04%); split: +0.26%, -0.31%

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35604>
 2025-07-13 10:39:53 +00:00