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radeonsi: add uses_kernelq_reg_shadowing in struct si_context

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sctx->uses_kernelq_reg_shadowing instead of sctx->shadowing.registers
for register shadowing enable check.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
This commit is contained in:
Yogesh Mohan Marimuthu
2025-06-11 12:38:34 +05:30
committed by Marge Bot
parent b55ee5f335
commit 1cb0af6308
7 changed files with 14 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
+2 -3
View File
@@ -11,8 +11,7 @@
bool si_init_cp_reg_shadowing(struct si_context *sctx)
{
if (sctx->is_gfx_queue &&
sctx->screen->info.has_kernelq_reg_shadowing) {
if (sctx->uses_kernelq_reg_shadowing) {
if (sctx->screen->info.has_fw_based_shadowing) {
sctx->shadowing.registers =
si_aligned_buffer_create(sctx->b.screen,
@@ -51,7 +50,7 @@ bool si_init_cp_reg_shadowing(struct si_context *sctx)
if (!si_init_gfx_preamble_state(sctx))
return false;
if (sctx->is_gfx_queue && sctx->screen->info.has_kernelq_reg_shadowing) {
if (sctx->uses_kernelq_reg_shadowing) {
/* We need to clear the shadowed reg buffer. */
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowing.registers->b.b,
0, sctx->shadowing.registers->bo_size, 0);
src/gallium/drivers/radeonsi/si_descriptors.c
+1 -1
View File
@@ -2166,7 +2166,7 @@ static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_de
radeon_emit_one_32bit_pointer(descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
} else if (sctx->gfx_level == GFX9 && sctx->shadowing.registers) {
} else if (sctx->gfx_level == GFX9 && sctx->uses_kernelq_reg_shadowing) {
/* We can't use the COMMON registers with register shadowing. */
radeon_emit_one_32bit_pointer(descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
src/gallium/drivers/radeonsi/si_gfx_cs.c
+2 -2
View File
@@ -512,7 +512,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer,
RADEON_USAGE_READ | RADEON_PRIO_BORDER_COLORS);
}
if (ctx->shadowing.registers) {
if (ctx->uses_kernelq_reg_shadowing) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->shadowing.registers,
RADEON_USAGE_READWRITE | RADEON_PRIO_DESCRIPTORS);
@@ -594,7 +594,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
if (ctx->screen->use_ngg_culling)
si_mark_atom_dirty(ctx, &ctx->atoms.s.ngg_cull_state);
if (first_cs || !ctx->shadowing.registers) {
if (first_cs || !ctx->uses_kernelq_reg_shadowing) {
/* These don't add any buffers, so skip them with shadowing. */
si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
/* CLEAR_STATE sets zeros. */
src/gallium/drivers/radeonsi/si_pipe.c
+3
View File
@@ -523,6 +523,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
!sscreen->info.ip[AMD_IP_COMPUTE].num_queues ||
!(flags & PIPE_CONTEXT_COMPUTE_ONLY);
if (sctx->is_gfx_queue)
sctx->uses_kernelq_reg_shadowing = sscreen->info.has_kernelq_reg_shadowing;
if (flags & PIPE_CONTEXT_DEBUG)
sscreen->record_llvm_ir = true; /* racy but not critical */
src/gallium/drivers/radeonsi/si_pipe.h
+1
View File
@@ -1001,6 +1001,7 @@ struct si_context {
bool suppress_update_ps_colorbuf0_slot:1;
bool is_noop:1;
bool is_gfx_queue:1;
bool uses_kernelq_reg_shadowing:1;
bool gfx_flush_in_progress : 1;
bool gfx_last_ib_is_busy : 1;
bool compute_is_busy : 1;
src/gallium/drivers/radeonsi/si_state.c
+3 -3
View File
@@ -5019,7 +5019,7 @@ static bool gfx6_init_gfx_preamble_state(struct si_context *sctx)
return false;
}
if (sctx->is_gfx_queue && !sctx->shadowing.registers) {
if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
@@ -5105,7 +5105,7 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx)
return false;
}
if (sctx->is_gfx_queue && !sctx->shadowing.registers) {
if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
@@ -5177,7 +5177,7 @@ static bool gfx12_init_gfx_preamble_state(struct si_context *sctx)
return false;
}
if (sctx->is_gfx_queue && !sctx->shadowing.registers) {
if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
src/gallium/drivers/radeonsi/si_state_shaders.cpp
+2 -2
View File
@@ -4079,7 +4079,7 @@ static void si_cs_preamble_add_vgt_flush(struct si_context *sctx, bool tmz)
&sctx->cs_preamble_has_vgt_flush;
/* We shouldn't get here if registers are shadowed. */
assert(!sctx->shadowing.registers);
assert(!sctx->uses_kernelq_reg_shadowing);
if (*has_vgt_flush)
return;
@@ -4202,7 +4202,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
false, 0, 0, 0);
}
if (sctx->shadowing.registers) {
if (sctx->uses_kernelq_reg_shadowing) {
/* These registers will be shadowed, so set them only once. */
struct radeon_cmdbuf *cs = &sctx->gfx_cs;