595a7f7c47
radeonsi/gfx10: add pipe_screen::make_texture_descriptor
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Texture descriptors in gfx10 are very different.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
4afce5efdd
radeonsi/gfx10: determine view->is_integer based on the pipe_format
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It was convenient, but NUM_FORMAT no longer exists in gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
3163db3ba4
radeonsi/gfx10: implement si_is_format_supported
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
0ffa2292b3
radeonsi/gfx10: generate gfx10_format_table.h
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
af29ad7cc6
radeonsi/gfx10: set MAX_ALLOC_COUNT
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The number for Vega was copied from PAL and has no effect because of MIN2.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
594010e366
radeonsi/gfx10: require LLVM 9
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
de99e0a563
radeon/vcn: update for new vcn enc interface
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
9ab1e427bb
radeonsi: enable jpeg decode for navi10
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
6480c7b577
radeon/vcn: implement vcn 2.0 jpeg decode
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Use direct register to implement vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
0cd7953ece
radeon/vcn: add direct register bool
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VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
7a5c22d32a
radeon/vcn: add defines for vcn 2.0 jpeg
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Add neccesary register defines for vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
0c27971157
radeon/vcn: use variable to assign ib cmd
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
587b9c5dae
radeon/vcn: implement vcn 2.0 encode
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
40e1bed389
radeon/vcn: add vcn2.0 encode skeleton
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
(v2: build fix -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
8f6272d494
radeon/vcn: move vcn1.0 specific defines to c
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
b5287a9fa6
radeon/vcn: assign function pointer with ib functions
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
9940a6e066
radeon/vcn: add function pointer for ib functions
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
c6b5188505
radeon/vcn: move header related algorithm to vcn_enc
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
dd46740bc2
radeon/vcn: move add buf func to common file
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
e6ca4d1bd8
radeon/vcn: move cs defines to enc header file
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
874881b26b
radeon/vcn: add VP9 support for Navi10
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It requires bigger DPB and context buffers
Signed-off-by: Leo Liu <leo.liu@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
9bbb546c4f
radeonsi: enable encode support for newer HW
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Previously it was Raven only allowed to do so
Signed-off-by: Leo Liu <leo.liu@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
d6acd29c9a
radeon/vcn: add VCN2 set of internal registers for IB
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From VCN2.0, the RBC have different views on the registers
Signed-off-by: Leo Liu <leo.liu@amd.com >
(v2: rebase -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
a38268ea5b
radeonsi/uvd: allow newer HW to create HW decoder
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Previously it was Raven only allowed to do so
Signed-off-by: Leo Liu <leo.liu@amd.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
84e7ee421f
ac/surface/gfx10: allow "rotated" micro mode
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Standard mode does not support DCC.
The R is retconned to "render target" on gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
a66be784c3
ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modes
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
97ddcfff7c
amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not support
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
9eb4a79345
amd/addrlib/gfx10: fix assertion in Addr2IsValidDisplaySwizzleMode
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
6d416ac7e1
amd/common/gfx10: print gfx10 registers in debug dumps
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
70fd27d1e3
amd/common/gfx10: CMASK is only used for FMASK
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All regular color compression is done via DCC.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
b52bf8f12a
amd/common/gfx10: support new tbuffer encoding
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
c067aaa580
amd/common/gfx10: pad shader buffers for instruction prefetch
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
227c29a80d
amd/common/gfx10: implement scan & reduce operations
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
7ba80c1d19
amd/common/gfx10: add GS_ALLOC_REQ message define
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
4c364c89e2
amd/common/gfx10: print out GCR_CNTL as part of {ACQUIRE,RELEASE}_MEM
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
74a26af913
amd/common/gfx10: add register JSON
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A small number of fields now need new disambiguation.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
536782b0b7
amd/common: add GFX10 chips
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
677bb80c98
meson: require libdrm_amdgpu 2.4.99 for Navi
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
db7e7a6cb5
radv: gfx10 is not supported
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
78cdf9a99f
amd/addrlib: add gfx10 support
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
112bf7f900
radeonsi: make emit_streamout_output externally accessible
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
e241b405ca
radeonsi: pass the context to query destroy functions
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We'll need this in the future.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
064f195ef0
radeonsi: make si_restore_qbo_state externally available
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
04e27ec136
radeonsi: make get_primitive_id externally visible
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
5059a4df8a
radeonsi: make si_llvm_export_vs externally available
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
4a774ba893
radeonsi: various si_translate_*format functions only apply to pre-gfx10
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
2019-07-03 15:51:12 -04:00
c53e6ea05d
radeonsi: use a fragment shader blit instead of DB->CB copy for ZS CPU mappings
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This mainly removes and simplifies code that is no longer needed.
There were some issues with the DB->CB stencil copy on gfx10, so let's
just use a fragment shader blit for all ZS mappings. It's more reliable.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de >
2019-07-03 15:51:12 -04:00
6686d8a130
gallium/u_blitter: implement copying from ZS to color and vice versa
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This is for drivers that can't map depth and stencil and need to blit
them to a color texture for CPU access.
This also useful for drivers using separate depth and stencil.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de >
2019-07-03 15:51:12 -04:00
13a5e9d685
gallium/util: rewrite depth-stencil blit shaders
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- merge all 3 functions (Z, S, ZS)
- don't write the color output
- read the value from texel.x, then write it to position.z or stencil.y
(don't use the value from texel.y or texel.z)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de >
2019-07-03 15:51:12 -04:00
131d40cfc9
st/mesa: accelerate glCopyPixels(STENCIL)
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Tested-by: Dieter Nützel
2019-07-03 15:50:04 -04:00
Nicolai Hähnle