Commit Graph

92185 Commits

Author SHA1 Message Date
Zack Rusin 3975f34fd3 Implement basic opcode translation and storage translation. 2007-10-24 11:21:03 -04:00
Zack Rusin fa2962d148 Draw first triangle. Start on the llvm builder. 2007-10-24 11:21:03 -04:00
Zack Rusin 5e0205023e Cleanup some of the testing code. Implement first pass at actually
running shaders in llvm.
2007-10-24 11:21:03 -04:00
Zack Rusin 5ffdada717 Execution engine is a singleton, for now keep it in the pipe. 2007-10-24 11:21:03 -04:00
Zack Rusin 9e6d58fac2 Generate the base shader. 2007-10-24 11:21:03 -04:00
Zack Rusin 2dbba8b024 Implement the conversion and do the initial execution pass. 2007-10-24 11:21:03 -04:00
Zack Rusin 11bc1f015a Stub out some conversion. 2007-10-24 11:21:03 -04:00
Zack Rusin b2e529982e Initial stab at LLVM integration. 2007-10-24 11:21:03 -04:00
Brian 4664261f8d Fix vertex cache bug that allows multiple vertices to fall into the same slot.
Need to set the slot's bit in draw->vcache.referenced even when there was a
cache hit since flushing the primitive buffer will have cleared the bitfield
but not the cache's vertex indexes.

Fixes a bug found when drawing long triangle fans but could be hit by other
prim types as well.

An alternate fix would be to call draw_vertex_cache_invalidate() from
draw_vertex_cache_unreference().
2007-10-23 15:08:54 -06:00
Brian 3df65af849 added comment 2007-10-23 15:02:02 -06:00
Brian 40e46d0727 In get_vertex(), slot was computed using & 31. Replace with % VCACHE_SIZE.
Also, assert that index is not too large before indexing array.
2007-10-23 12:32:02 -06:00
Brian be04999982 adjust coords in wide_line() to be conformant 2007-10-23 11:38:17 -06:00
Brian c9d495c6f0 properly init dst reg's CondMask/Swizzle fields 2007-10-23 10:55:24 -06:00
Brian 112a1580f6 properly init dst reg's CondMask/Swizzle fields 2007-10-23 10:54:50 -06:00
Brian 2a8e9bb00f bump up MAX_INSTRUCTIONS and add an assertion to catch emitting too many instructions 2007-10-23 10:24:53 -06:00
Brian e69943e6dd bump up MAX_INSTRUCTIONS and add an assertion to catch emitting too many instructions 2007-10-23 10:23:01 -06:00
Brian 5c79c088cd Don't pad renderbuffers to multiple of two pixels anymore.
This was only needed to avoid out-of-bounds memory accesses with the
2x2 quad_read/write() functions which no longer exist.
2007-10-23 08:30:36 -06:00
Brian e90dd4bf8f add directfb glut sources to tarball 2007-10-23 08:22:21 -06:00
Brian 2667e5642f don't apply ColorMask to main gc 2007-10-22 17:50:59 -06:00
Brian 588c91eb0a don't apply ColorMask to main gc 2007-10-22 17:50:00 -06:00
Brian 455a08d87d fix masking bug, memory leak 2007-10-22 17:20:56 -06:00
Brian 0a3eaeadb9 don't use GL types for get/put_tile() params 2007-10-22 17:20:08 -06:00
Brian beefc6011b new flag to control psize (from vertex shader or fixed size) 2007-10-22 12:19:54 -06:00
Brian 1b48523459 add support for sprite texcoord modes 2007-10-22 12:10:30 -06:00
Brian 22e5c4f0f0 implement point sprite mode 2007-10-22 11:59:26 -06:00
Brian cd4d732773 add point_sprite flag to rasterizer state 2007-10-22 11:41:31 -06:00
Brian 34abb93ea1 remove unused var 2007-10-22 11:41:17 -06:00
Brian 8d24415987 tweak point corners to pass conform test 2007-10-22 11:38:40 -06:00
Brian e3444deec5 plug the wide prims code into the pipeline 2007-10-22 11:01:34 -06:00
Brian 80d2bb7c64 update to working condition 2007-10-22 11:01:02 -06:00
Brian 70eb7996f2 Finish unifying the surface and texture tile caches. 2007-10-22 09:37:26 -06:00
keithw ec3bd21c46 pull clip/ module wide and stippled lines/points code 2007-10-22 15:24:42 +01:00
Brian b3204c2aff Start implementing cache routines for textures.
First step to consolidating surface/texture caching...
2007-10-21 18:06:35 -06:00
Brian c2322333b8 rename some vars 2007-10-21 17:15:07 -06:00
Brian cae640eae6 silence warning 2007-10-21 17:14:46 -06:00
Brian 49848208cf Remove obsolete read/write_quad() functions 2007-10-20 16:09:17 -06:00
Brian 03145d864c init sp->sbuf_cache to avoid possible segfault 2007-10-20 15:52:59 -06:00
Brian f9aa757187 Call softpipe_unmap_surfaces() in softpipe_flush().
This fixes a DRM BO failure upon swapbuffers caused by the color buffer
still being mapped.
This is a bit heavy handed since we don't always need to unmap buffers
when flushing.  Need to pass a flag to flush() or design a new function.
2007-10-20 15:52:36 -06:00
Brian 7c8b2f7ce3 In region_unmap(), check if region is mapped before decrementing refcount. 2007-10-20 15:45:24 -06:00
Brian bb3d61551c flush the pipe before accum ops 2007-10-20 15:21:02 -06:00
Brian a1633c0716 unmap regions when reallocating renderbuffer storage 2007-10-20 15:20:46 -06:00
Brian fd3876e9e3 renderbuffer tweaks in update_framebuffer_state() 2007-10-20 15:20:17 -06:00
Brian 46e2d2bb0a use combined depth/stencil buffer when possible 2007-10-20 15:19:14 -06:00
Brian 7e83963998 Convert Z/stencil ops to use cached tiles like colors.
Also, quite a bit of re-org of the tile caches and surface mapping/unmapping.
Leave surfaces mapped between primitives now.
2007-10-20 15:18:02 -06:00
Brian 832e73bc09 added case for TGSI_OPCODE_END 2007-10-20 10:09:12 -06:00
Brian c492725abf get/put_tile_raw() funcs for 16/32bpp surfaces 2007-10-19 12:47:05 -06:00
Brian d4a9d4bdef added get/put_tile_raw() methods 2007-10-19 12:45:54 -06:00
Brian ffd37b1fda don't alloc region in xmesa_surface_alloc(), fixes a mem leak 2007-10-19 12:42:05 -06:00
Brian 257f0da6a2 disable debug printf 2007-10-19 10:13:55 -06:00
Brian 96b06ac557 call Driver.Flush() in _mesa_notifySwapBuffers() 2007-10-19 10:12:00 -06:00